MIC2184 Datasheet, PDF (4/12 Pages) Micrel Semiconductor – Low Voltage Buck PWM Control IC Final Information

MIC2184
Micrel
Absolute Maximum Ratings (Note 1)
Supply Voltage (V_INA, V_INP) ......................................... 15V
Digital Supply Voltage (V_DD) ........................................... 7V
Comp Pin Voltage (V_COMP) ............................ –0.3V to +3V
Feedback Pin Voltage (V_FB) .......................... –0.3V to +3V
Enable Pin Voltage (V_EN/UVLO) ..................... –0.3V to 15V
Current Sense Voltage (V_CSH–V_CSL) ............... –0.3V to 1V
Sync Pin Voltage (V_SYNC) ................................ –0.3V to 7V
Freq/2 Pin Voltage (V_FREQ/2) ............................ -0.3V to 7V
Power Dissipation (P_D)
16 lead SOIC ................................. 400mW @ T_A = 85°C
16 lead QSOP ............................... 245mW @ T_A = 80°C
Ambient Storage Temp ............................ –65°C to +150°C
ESD Rating, ............................................................. Note 3
Electrical Characteristics
Operating Ratings (Note 2)
Supply Voltage (V_INA, V_INP) ........................ +2.9V to +14V
Ambient Operating Temperature ......... –40°C ≤ T_A ≤ +85°C
Junction Temperature ....................... –40°C ≤ T_J ≤ +125°C
Output Voltage Range ...................................... 1.3V to 12V
PackageThermal Resistance
θ_JA 16-lead SOP ............................................... 100°C/W
θ_JA 16-lead QSOP ............................................. 163°C/W
V_INA = V_INP = V_CSH = 5V, V_OUT = 3.3V, V_EN/UVLO = 5V, V_FREQ/2 = 0V, T_J = 25ºC, unless otherwise specified. Bold values indicate
–40ºC < T_J < +125ºC.
Parameter
Condition
Min Typ Max Units
Regulation
Feedback Voltage Reference
(±1%)
(±2%)
1.233 1.245 1.257 V
1.22
1.27
V
Feedback Bias Current
50
nA
Output Voltage Line Regulation
Output Voltage Load Regulation
Output Voltage Total Regulation
Input & V_DD Supply
V_INA Input Current
V_INP Input Current, Note 4
Shutdown Quiescent Current
Digital Supply Voltage (V_DD)
Digital Supply load regulation
Undervoltage Lockout
UVLO Hysteresis
5V ≤ V_IN ≤ 12V
0mV < (V_CSH – V_CSL) < 75mV
5V ≤ V_INA ≤ 12V, 0mV < (V_CSH – V_CSL) < 75mV (±3%)
(Excluding external MOSFET gate current)
V_EN/UVLO = 0V; (I_VINA + I_VINP)
I_L = 0
I_L = 0 to 1mA
V_DD upper threshold (turn on threshold)
0.04
%/V
0.9
%
1.208
1.282 V
0.7
mA
1.0
mA
0.5
5
µA
2.82 3.0 3.18
V
0.03
V
2.75
V
100
mV
Reference Output(VREF)
Reference Voltage
(±1.5%)
(±2.5%)
1.226 1.245 1.264 V
1.213
1.276 V
Reference Voltage Line
Regulation
5V < V_INA < 12V
2
mV
Reference Voltage Load
Regulation
0 < I_REF < 100µA
1
mV
Enable/UVLO
Enable Input Threshold
0.6
0.9
1.2
V
UVLO Threshold
(Turn-on threshold)
1.4
1.5
1.6
V
UVLO Hysteresis
140
mV
Enable Input Current
V_EN/UVLO = 5V
0.2
5
µA
MIC2184
4
December 10, 2001