DSC2011FM2-E0015 Datasheet, PDF (4/6 Pages) Micrel Semiconductor – Crystal-less™ Configurable Clock Generator

Micrel, Inc.
DSC2011FM2-E0015
Specifications (Unless specified otherwise: T = 25°C, max LVCMOS drive strength)
Parameter
Supply Voltage¹
Supply Current
Supply Current²
Symbol
VDD
VDD2
IDD
IDD
Frequency Stability
F
Aging
F
Startup Time³
tSU
Input Logic Levels
Input Logic High
VIH
Input Logic Low
VIL
Output Disable Time⁴
tDA
Output Enable Time
tEN
Pull-Up Resistor²
Output Logic Levels
Output Logic High
Output Logic Low
VOH
VOL
Output Transition Time⁴
Rise Time
tR
Fall Time
tF
Frequency
CLK1
CLK2
Output Duty Cycle
Period Jitter⁵
SYM
JPER
Integrated Phase Noise JPH
Condition
VDD2 ≤ VDD
OE pin low - outputs are disabled
OE pin high - outputs are enabled
CL = 15pF, F01 = F02 = 125MHz
Includes frequency variation due to initial
tolerance, temp. and power supply voltage
First year (@ 25°C)
T = 25°C
Pull-up exists on all digital IO
LVCMOS Outputs
I = ±6mA
20% to 80%
CL = 15pF
[FS2, FS1, FS0] = [1, 1, 1]
F01 = F02 = 125MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
Min.
2.25
1.65
0.75 x VDD
-
0.9 x VDD
-
45
Typ.
21
32
40
1.1
1.4
20
20
3
0.3
0.38
1.7
Max.
3.6
3.6
23
Units
V
mA
mA
±25
ppm
±5
ppm
5
ms
-
0.25 x VDD V
5
ns
20
ns
kOhms
-
V
0.1 x VDD
2
2
ns
MHz
55
%
psRMS
psRMS
2
Notes:
1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors.
2. Output is enabled if OE pin is floated or not connected.
3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Test Circuit figures below define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
May 10, 2016
4
3892
Revision 1.0
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