MIC2829 Datasheet, PDF (31/52 Pages) Micrel Semiconductor – 3G/4G HEDGE/LTE PMIC with Six Buck Converters, Eleven LDOs and SIM Card Level Translation

Micrel Inc.
ENGLB
The global enable pin (ENGLB) must be pulled high in
order for the MIC2829 to function. When ENGLB is
pulled high, a startup sequence begins. The regulators
DC1, DC3, DC4/LDO2, LDO1/LDO11 turn on in
sequence. See Turn-ON Sequence Flow Chart in Figure
1.
Figure 1. Turn-ON Sequence Flow Chart
ENDC
ENGLB needs to be high in order for any other enables
to function. A logic high signal on the enable pin
(ENDC2, ENDC5, ENDC6) activates the output voltage
of its respective buck regulator shown in Table 1. A logic
low signal on the enable pin deactivates the output of the
buck regulator. Do not leave floating, as it would leave
the regulator in an unknown state.
MIC2829
ENDC
ENDC2
ENDC5
ENDC6
HIGH (>1.1V)
DC2 ON
DC5 ON
DC6 ON
LOW (<0.2V)
DC2 OFF
DC5 OFF
DC6 OFF
Table 1. Buck Regulator Enable
ENL
ENGLB needs to be high in order for any other enables
to function. A logic high signal on the enable pin (ENL3
to ENL8, ENL910) activates the output voltage of LDO3,
LDO4 and LNR5 to LNR10 as shown in Table 2. A logic
low signal on the enable pin deactivates the output of the
respective LDO. Do not leave floating, as it would leave
the regulator in an unknown state.
ENL
ENL3
ENL4
ENL5
ENL6
ENL7
ENL8
ENL910
HIGH (>1.1V)
LDO3 ON
LDO4 ON
LNR5 ON
LNR6 ON
LNR7 ON
LNR8 ON
LNR9, LNR10 ON
LOW (<0.2V)
LDO3 OFF
LDO4 OFF
LNR5 OFF
LNR6 OFF
LNR7 OFF
LNR8 OFF
LNR9, LNR10 OFF
Table 2. LDO Regulator Enable
SETDLY
If the output voltage of DC4 is greater than 90% of
nominal, the Power On Reset (POR) delay circuit begins
to source a current to the set-delay pin (SETDLY). The
SETDLY pin is used to adjust the delay time of the
RESETB flag. A capacitor may be placed from SETDLY
to ground (AGND1, AGND2) to adjust the delay time at a
rate of 1 second/µF.
RESETB
The RESETB is an open drain output and can, for
instance, be tied to the output of DC4 through a 100k
resistor. When DC4 output voltage is greater than 96%,
then the RESETB voltage will be pulled high after a
delay set by the capacitor on the SETDLY pin. A
capacitor at the SETDLY pin will delay the RESETB flag
at a rate of 1 second / µF. When the output of DC4 is
below 90%, RESETB is pulled low.
FB1 to FB4
The feedback pin (FB1 to FB4) is connected to the
output of the HyperLight Load^TM circuit to provide
feedback to the control circuitry. The FB connection
should be connected close to the output capacitor. Refer
to the layout recommendations for more details.
May 2010
31
M9999-051410-B