MIC2782_12 Datasheet, PDF (3/16 Pages) Micrel Semiconductor – Dual-Input Push Button Reset IC with Immediate and Delayed Outputs

Micrel, Inc.
Chip Scale Package (CS) Bump Configuration
MIC2782
Y = Year Code
WW = Week Code
TOP VIEW
TOP VIEW (BUMP SIDE DOWN)
BOTTOM VIEW (BUMP SIDE UP)
6-Bump, 0.4mm pitch, 0.8mm x 1.2mm WLCSP Package
Bump
Designation
A1
A2
B1
B2
C1
C2
Bump
Name
ANDOUT
/MR2
RESET
/MR1
VDD
GND
Pin Function
NMOS Open-Drain output, Active-Low. Asserts low 1.5ms after /MR1 and /MR2 are both asserted low.
Connect a resistor greater than 5k from the ANDOUT pin to VDD in order to pull up the ANDOUT
output voltage when inactive. No ESD diode from ANDOUT to VDD. Please see the Functional
Description and Timing Diagram sections for further details of how the ANDOUT output functions.
Manual Reset Input 2, Active-Low. Internal 65k (typical) Pull-Up Resistor to VDD. Pulling both manual
reset inputs low for longer than the setup period causes one RESET output pulse for the reset timeout
delay period.
NMOS Open-Drain output, Active-Low. Asserts low after /MR1 and /MR2 have both asserted low for
longer than setup period. Connect a resistor greater than 5k from the RESET pin to VDD in order to
pull up the RESET output voltage when inactive. No ESD diode from RESET to VDD. Please see the
Functional Description and Timing Diagram sections for further details of how the RESET output
functions.
Manual Reset Input 1, Active-Low. Internal 65k (typical) Pull-Up Resistor to VDD. Pulling both manual
reset inputs low for longer than the setup period causes one RESET output pulse for the reset timeout
delay period.
Supply Voltage. Bypass to ground with minimum 0.1µF capacitor.
Supply Ground.
January 2012
3
M9999-010912-A