MIC26903ZA Datasheet, PDF (3/28 Pages) Micrel Semiconductor – 28V, 9A Hyper Speed Control Synchronous DC/DC Buck Regulator

Micrel, Inc.
MIC26903-ZA
Pin Description
Pin Number
1
2, 5, 6, 7, 8,
21
3
4, 9, 10, 11,
12
13,14,15,16,
17,18,19
20
22
23
24
25
26
27
28
Pin Name
PVDD
PGND
NC
SW
PVIN
BST
CS
SGND
FB
PG
EN
VIN
VDD
Pin Function
5V Internal Linear Regulator output: PVDD supply is the power MOSFET gate drive supply voltage
created by internal LDO from VIN. When VIN < +5.5V, PVDD should be tied to the PVIN pins. A 2.2µF
ceramic capacitor from the PVDD pin to PGND (pin 2) must be placed next to the IC.
Power Ground: PGND is the ground path for the buck converter power stage. The PGND pins connect
to the low-side N-Channel internal MOSFET gate drive supply ground, the sources of the MOSFETs,
the negative terminals of input capacitors, and the negative terminals of output capacitors. The loop
for the power ground should be as small as possible and separate from the signal ground (SGND)
loop.
No Connect.
Switch Node output: Internal connection for the high-side MOSFET source and low-side MOSFET
drain. Because of the high-speed switching on this pin, the SW pin should be routed away from
sensitive nodes.
High-Side N-Internal MOSFET Drain Connection input: The PVIN operating voltage range is from 4.5V
to 28V. Input capacitors between the PVIN pins and the power ground (PGND) are required and keep
the connection short.
Boost output: Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is
connected between the PVDD pin and the BST pin. A boost capacitor of 0.1μF is connected between
the BST pin and the SW pin. Adding a small resistor at the BST pin can reduce the turn-on time of
high-side N-Channel MOSFETs.
Current Sense input: The CS pin senses current by monitoring the voltage across the low-side
MOSFET during the OFF-time. The current sensing is necessary for short circuit protection. To sense
the current accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. The CS
pin is also the high-side MOSFET’s output driver return.
Signal Ground: SGND must be connected directly to the ground planes. Do not route the SGND pin to
the PGND pad on the top layer (see “PCB Layout Guidelines” for details).
Feedback input: Input to the transconductance amplifier of the control loop. The FB pin is regulated to
0.6V. A resistor divider connecting the feedback to the output is used to adjust the desired output
voltage.
Power Good output: Open drain output. The PG pin is externally tied with a resistor to VDD. A high
output is asserted when VOUT > 92% of nominal.
Enable input: A logic level control of the output. The EN pin is CMOS-compatible. Logic high = enable,
logic low = shutdown. In the off state, the supply current of the device is greatly reduced (typically
5µA). Do not leave the EN pin open.
Power Supply Voltage input: Requires a bypass capacitor to SGND.
5V Internal Linear Regulator output: VDD supply is the power MOSFET gate drive supply voltage and
the supply bus for the IC. VDD is created by internal LDO from VIN. When VIN < +5.5V, VDD should
be tied to PVIN pins. A 1µF ceramic capacitor from the VDD pin to SGND pins must be placed next to
the IC.
May 29, 2013
3
Revision 1.0