DSC2111FL2-E0018 Datasheet, PDF (3/6 Pages) Micrel Semiconductor – Crystal-less™ Configurable Clock Generator

Micrel, Inc.
Operational Description
The DSC2111FL2-E0018 is a dual output LVCMOS
oscillator consisting of a MEMS resonator and a supporting
PLL IC. The two LVCMOS outputs are generated through
independent 8-bit programmable dividers from the output
of the internal PLL. DSC2111FL2-E0018 allows for easy
programming of theoutput frequencies using I2C interface.
Upon power-up, the output frequencies are controlled
by an internal pre-programmed memory (OTP). This
memory stores all coefficients required by the PLL for two
different default frequency pairs. The control pin (FS)
selects the initial pair. Once the device is powered up, a
new output frequency pair can be programmed using I2C
pins. Programming details are provided in the
Programming Guide.
DSC2111FL2-E0018
The DSC2111FL2-E0018 has independent control of the
output voltage levels of the two outputs. The high voltage
level of CLK1 is equal to the main supply voltage, VDD
(pin 13). VDD2 (pin 12) sets the high voltage level of
CLK2. VDD2 must be equal to or less than VDD at all
times to insure proper operation. VDD2 can be as low
as 1.65V. When OE (pin 1) is floated or connected to
VDD, the DSC2111FL2-E0018 is in operational mode.
Driving OE to ground will disable both output
drivers (hi-impedance mode).
DSC2111FL2-E0018 has programmable output drive
strength, which can be controlled via I2C.
Table 1 displays typical rise / fall times for the output
with a 15pF load capacitance as a function of these
control bits at VDD = 3.3V and room temperature.
tr (ns)
tf (ns)
Output Drive Strength Bits [OXS2, OXS1, OXS0] - Default is [111] - X = 1 for CLK1, and 2 for CLK2
000
001
010
011
100
101
110
111
2.1
1.7
1.6
1.4
1.3
1.3
1.2
1.1
2.5
2.4
2.4
2
1.8
1.6
1.3
1.3
Table 1. Rise/Fall Times for Drive Strengths
Output Clock Frequencies
Frequency select bits are weakly tied high so if left unconnected the default setting will be [1] and the device will output the
associated frequency highlighted in bold.
Freq (MHz)
CLK1
CLK2
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
1000+ years of data retention on internal memory
May 11, 2015
2972
Freq Select Bit [FS] - Default is [1]
0
1
27
25
24
125
Table 2. Pin-Selectable Output Frequencies
Min.
-0.3
-0.3
-
-55
-
-
3
Max.
+4.0
VDD + 0.3
+150
+150
+260
4000
400
1500
Units
V
V
°C
°C
°C
V
Condition
40sec max.
Revision 1.0
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