KSZ8051MNLV Datasheet, PDF (27/66 Pages) Micrel Semiconductor – 10Base-T/100Base-TX Physical Layer Transceiver

Micrel, Inc.
KSZ8051MNLV/KSZ8051RNLV
RMII Back-to-Back Mode (KSZ8051RNLV only)
In RMII back-to-back mode, a KSZ8051RNLV interfaces with another KSZ8051RNLV to provide a complete 100Mbps
copper repeater solution.
The KSZ8051RNLV devices are configured to RMII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to 101
• A common 50MHz reference clock connected to XI (pin 9) of both KSZ8051RNLV devices
• RMII signals connected as shown in Table 4
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8051RNLV (100Base-TX copper)
[Device 1]
KSZ8051RNLV (100Base-TX copper)
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
18
Output
TXEN
23
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
CRSDV
18
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
MII Management (MIIM) Interface
The KSZ8051MNLV/RNLV supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8051MNLV/RNLV. An external device with MIIM capability is used to read the PHY status
and/or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external
controller to communicate with one or more PHY devices.
• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See the “Register Map”
section for details.
As the default, the KSZ8051MNLV/RNLV supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The
latter is defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNLV/RNLV device,
or write to multiple KSZ8051MNLV/RNLV devices simultaneously.
PHY address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin
19) or software (register 16h, bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each
KSZ8051MNLV/RNLV device.
August 27, 2015
27
Revision 1.0