MICRF507 Datasheet, PDF (25/46 Pages) Micrel Semiconductor – 470MHz to 510MHz Low-Power FSK Transceiver with +10dBm Power Amplifier

Micrel, Inc.
MICRF507
The front end’s input impedance, with no matching
network, is close to 50Ω as shown in Figure 15. This gives
an input reflection coefficient of about -13dB. Although the
receiver does not require a matching network to optimize
the gain, a matching network is recommended for
harmonic suppression during transmission and for
improved selectivity in reception.
Sallen-Key Filters
Each IF channel includes a pre-amplifier and a pre-filter.
The preamplifier has a gain of 22dB. The IF amplifier also
removes DC offset. Gain varies by less than 0.5dB over a
2.0V to 2.5V variation in power supply.
The pre-filter is implemented as a three-pole Sallen-Key
low-pass filter. It protects the switched-capacitor filter that
follows it from strong adjacent channel signals and also
serves as an anti-aliasing filter. It is programmable to four
different cut-off frequencies as shown in Table 14.
PF_FC1
0
0
1
1
PF_FC0
0
1
0
1
Cutoff (3dB filter corner)
100kHz
150kHz
230kHz
340kHz
Table 14. Pre-Filter Bit Field
Switched Capacitor Filter
The main IF channel filter is a switched-capacitor
implementation of a six-pole elliptic low pass filter. This
meets selectivity and dynamic range requirements with
minimum total capacitance. The cut-off frequency of the
switched-capacitor filter is adjustable by changing the
clock frequency.
A 6-bit frequency divider, programmed by the ScClk[5:0]
field, is clocked by the crystal oscillator. Its output, which is
20 times the filter’s cutoff frequency, is then divided by 4 to
generate the correct non-overlapping clock phases needed
by the filter. The cut-off frequency of the filter is given by:
f_CUT
=
f _XCO
40 ⋅ ScClk
f_CUT: Filter cutoff frequency
f_XCO: Crystal oscillator frequency
ScClk: Switched capacitor filter clock, bits ScClk[4:0]
(bit 0 has a mandatory value of ‘0’).
For instance, for a crystal frequency of 16MHz and if the 6
bit divider divides the input frequency by 4, the cut-off
frequency of the SC filter is 16MHz/(40 x 4) = 100kHz. A
first-order RC low-pass filter removes clock frequency
components from the signal at the switched-capacitor filter
output.
The pre-filter and switched-capacitor filters in cascade
must pass the full IF bandwidth of the received signal. In a
zero-IF receiver such as the MICRF507 this bandwidth is
as follows:
f_BW
=
f _OFFSET
+
f_DEV
+
r_b
2
where
f_BW: Needed receiver bandwidth; f_CUT above should
not be smaller than f_BW [Hz]
f_OFFSET: Total frequency offset between receiver and
transmitter [Hz]
f_DEV: Single-sided frequency deviation [Hz]
r_b: The bit rate in bits/sec
RSSI
RSSI
33kohm, 1nF, 125kbps, BW=200kHz, Vdd=2.5V
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25
Pin [dBm]
Figure 16. RSSI Voltage
Pin 14
RSSI
R2
33k
RSSI
C10
1nF
Figure 17. RSSI Network
Figure 16 shows a typical plot of the RSSI voltage as a
function of input power. The RSSI termination network is
shown in Figure 17. The RSSI has a dynamic range of
about 50dB from about -110dBm to -60dBm input power.
When an RF signal is received, the RSSI output increases
and can serve as a signal presence indicator. It could be
used to wake up external circuitry that conserves battery
life while in a sleep mode. Note that RSSI only functions in
Receive mode.
March 2010
25
M9999-032210-B