MIC2103_13 Datasheet, PDF (22/38 Pages) Micrel Semiconductor – 75V, Synchronous Buck Controllers featuring Adaptive On-Time Control

Micrel, Inc.
In case of hard short, the short limit is folded down to
allow an indefinite hard short on the output without any
destructive effect. It is mandatory to make sure that the
inductor current used to charge the output capacitance
during soft start is under the folded short limit, otherwise
the supply will go in hiccup mode and may not be
finishing the soft start successfully.
The MOSFET RDS(ON) varies 30 to 40% with temperature;
therefore, it is recommended to add a 50% margin to ICL
in the above equation to avoid false current limiting due
to increased MOSFET junction temperature rise. It is
also recommended to connect SW pin directly to the
drain of the low-side MOSFET to accurately sense the
MOSFETs RDS(ON).
MOSFET Gate Drive
The MIC2103/04 high-side drive circuit is designed to
switch an N-Channel MOSFET. Figure 1 shows a
bootstrap circuit, consisting of D1 (a Schottky diode is
recommended) and C_BST. This circuit supplies energy to
the high-side drive circuit. Capacitor C_BST is charged
while the low-side MOSFET is on and the voltage on the
SW pin is approximately 0V. When the high-side
MOSFET driver is turned on, energy from C_BST is used to
turn the MOSFET on. As the high-side MOSFET turns
on, the voltage on the SW pin increases to
approximately V_IN. Diode D1 is reverse biased and C_BST
floats high while continuing to keep the high-side
MOSFET on. The bias current of the high-side driver is
less than 10mA so a 0.1μF to 1μF is sufficient to hold
the gate voltage with minimal droop for the power stroke
(high-side switching) cycle, i.e., ΔBST = 10mA x
3.33μs/0.1μF = 333mV. When the low-side MOSFET is
turned back on, C_BST is recharged through D1. A small
resistor R_G, which is in series with C_BST, can be used to
slow down the turn-on time of the high-side N-channel
MOSFET.
The drive voltage is derived from the V_DD supply voltage.
The nominal low-side gate drive voltage is V_DD and the
nominal high-side gate drive voltage is approximately
V_DD – V_DIODE, where V_DIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side
and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both
MOSFETs.
November 26, 2013
22
MIC2103/04
Revision 2.0