KSZ8692PB Datasheet, PDF (22/46 Pages) Micrel Semiconductor – Integrated Networking and Communications Controller

Micrel, Inc.
KSZ8692PB, KSZ8692PB-S
Pin Descriptions-Power up Strapping Options (Continued)
Pin Number
G3
M1
J4
R3
Pin Name
SADDR[11]
EROEN
(WRSTPLS)
ERWEN0
NCLE
Pin Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Pin Description
During reset, this pin is input strap option to enable MII mode at port1 (LAN port)
0: MII mode (default)
1: Factory Reserved
ROM/SRAM/FLASH(NOR) and EXTIO Output Enable, asserted Low.
When asserted, this signal controls the output enable port of the specified
ROM/SRAM/FLASH memory and EXTIO device.
During reset, this pin is used for Watchdog Timer Reset Polarity Select.
This is a power strapping option pin for watchdog reset output polarity.
“0” = WRSTO is selected as active high (default)
“1” = WRSTO is selected as active low.
This pin is shared with the EROEN pin.
ROM/SRAM/FLASH(NOR) and EXTIO Write Byte Enable, asserted Low.
When asserted, these signals control the byte write enable of the memory device
for ROM/SRAM/FLASH and EXTIO access.
During ARM tic test mode, this pin is TESTACK.
During reset, this pin is input strap option to enable MII mode at port0 (WAN port)
0: MII mode (default)
1: Factory Reserved
NAND command Latch Enable
NCLE controls the activating path for command sent to NAND flash.
During reset, this pin is input strap option for NAND Flash configuration register
(0x8054) bit [2]. This bit along with configuration register bits [1:0] is used for boot
program. This pin along with NALE and NWEN is used to specify NAND Flash
size.
[NCLE, NALE, NWEN]
000 = 64Mbit
001 = 128Mbit (default)
010 = 256Mbit
011 = 512Mbit
100 = 1Gbit
101 = 2Gbit
110 = 4Gbit
111 = 8Gbit
(Not support NAND Boot)
May, 2011
22
M9999-051111-4.0