MIC2592B_05 Datasheet, PDF (21/31 Pages) Micrel Semiconductor – Dual-Slot PCI Express Hot-Plug Controller

MIC2592B
inputs are needed for diagnostic purposes, the
/FORCE_ON[A/B] inputs must be enabled; that is, CNTRL[A/B]
Register Bit D[2] should read Logical “0.” Once /FORCE_ON[A/B]
inputs are asserted, all output voltages are present with all
circuit protection features disabled, including overtemperature
protection on VAUX[A/B] outputs. To inhibit /FORCE_ON[A/B]
operation, a Logical “1” shall be written to the CNTRL[A/B]
Register Bit D[2] location(s).
HPI-only Control Applications
In applications where the MIC2592B is controlled only by the
HPI, SMBus signals SCL, SDA, and /INT signals are con-
nected to V_STBY as shown in Figure 6. In this configuration,
the MIC2592B’s /FAULT[A/B] outputs are activated after
power-on-reset and become asserted when:
Either or both external ON[A/B] and AUXEN[A/B] input signals
are asserted, AND
• 12VIN[A/B], 3VIN[A/B], or VSTBY[A/B] input volt-
age is lower than its respective ULVO threshold,
OR
• The fast OC circuit breaker[A/B] has tripped, OR
• The slow OC circuit breaker[A/B] has tripped AND
its filter timeout[A/B] has expired, OR
• The slow OC circuit breaker[A/B] has tripped AND
Slot[A/B] die temperature > 140°C, OR
• The MIC2592B’s global die temperature > 160°C
In order to clear /FAULT[A/B] outputs once asserted, either
or both ON[A/B] and AUXEN[A/B] input signals must be
deasserted. Please see /FAULT[A/B] pin description for ad-
ditional information.
If the /FORCE_ON[A/B] inputs are used for diagnostic pur-
poses, both /FAULT[A/B] and /PWRGD[A/B] outputs are
deasserted once /FORCE_ON[A/B] inputs are asserted.
Serial Port Operation
The MIC2592B uses standard SMBus Write_Byte and
Read_Byte operations for communication with its host. The
SMBus Write_Byte operation involves sending the device’s
target address, with the R/W bit (LSB) set to the low (write)
state, followed by a command byte and a data byte. The SMBus
Read_Byte operation is similar, but is a composite write and
read operation: the host first sends the device’s target address
followed by the command byte, as in a write operation. A new
“Start” bit must then be sent to the MIC2592B, followed by a
Micrel
repeat of the device address with the R/W bit set to the high
(read) state. The data to be read from the part may then be
clocked out. There is one exception to this rule: If the location
latched in the pointer register from the last write operation is
known to be correct (i.e., points to the desired register within
the MIC2592B), then the “Receive_Byte” procedure may be
used. To perform a Receive_Byte operation, the host sends
an address byte to select the target MIC2592B, with the R/W
bit set to the high (read) state, and then retrieves the data
byte. Figures 10 through 12 show the formats for these data
read and data write procedures.
The Command Register is eight bits (one byte) wide. This
byte carries the address of the MIC2592B’s register to be
operated upon. The command byte values corresponding to
the various MIC2592B register addresses are shown in Table
2. Command byte values other than 0000 0XXX_b = 00_h – 07_h
are reserved and should not be used.
MIC2592B SMBus Address Configuration
The MIC2592B responds to its own unique SMBus address,
which is assigned using A2, A1, and A0. These represent
the 3 LSBs of its 7-bit address, as shown in Table 3. These
address bits are assigned only during power up of the
VSTBY[A/B] supply input. These address bits allow up to
eight MIC2592B devices in a single system. These pins are
either grounded or left unconnected to specify a logical 0 or
logical 1, respectively. A pin designated as a logical 1 may
also be pulled up to V_STBY.
Inputs
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MIC2592B Device Address
Binary
Hex
1000 000X*_b
80_h
1000 001X_b
82_h
1000 010X_b
84_h
1000 011X_b
86_h
1000 100X_b
88_h
1000 101X_b
8A_h
1000 110X_b
8C_h
1000 111X_b
8E_h
* Where X = "1" for READ and "0" for Write
Table 3. MIC2592B SMBus Addressing
MIC2592B Register Set and Programmer’s Model
Target Register
Command Byte Value
Label
CNTRLA
CNTRLB
STATA
STATB
CS
Reserved
March 2005
Description
Read
Control Register Slot A
02_h
Control Register Slot B
03_h
Slot A Status
04_h
Slot B Status
05_h
Common Status Register
06_h
Reserved / Do Not Use
07h - FF_h
Table 2. MIC2592B Register Addresses
21
Write
02_h
03_h
04_h
05_h
06_h
07h - FF_h
Power-On
Default
00_h
00_h
00_h
00_h
xxxx 0000_b
Undefined
M9999-033105