SY89875U_0708 Datasheet, PDF (2/10 Pages) Micrel Semiconductor – 2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS

Micrel, Inc.
Precision Edge^®
SY89875U
PACKAGE/ORDERING INFORMATION
16 15 14 13
Q0 1
/Q0 2
Q1 3
/Q1 4
12 IN
11 VT
10 VREF-AC
9 /IN
5678
16-Pin MLF^® (MLF-16)
Ordering Information(1)
Part Number
Package Operating
Type
Range
Package
Marking
Lead
Finish
SY89875UMI
SY89875UMITR⁽²⁾
SY89875UMG⁽³⁾
MLF-16
MLF-16
MLF-16
SY89875UMGTR^{(2, 3)} MLF-16
Industrial
Industrial
Industrial
Industrial
875U
875U
875U with
Pb-Free bar line indicator
875U with
Pb-Free bar line indicator
Sn-Pb
Sn-Pb
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T_A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number
12, 9
1, 2, 3, 4
16, 15, 5
6
8
10
11
7, 14
13
Pin Name
IN, /IN
Q0, /Q0
Q1, /Q1
S0, S1, S2
NC
/RESET,
/DISABLE
VREF-AC
VT
VCC
GND
Exposed
Pin Function
Differential Input: Internal 50ý termination resistors to V_T input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Unused output pairs must be terminated with 100ý across the different pair.
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is V_CC/2.
No Connect.
LVTTL/CMOS Logic Levels: Internal 25ký pull-up resistor. Logic HIGH if left unconnected.
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is V_CC/2.
Reference Voltage: Equal to V_CC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the V_REF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f, “Input Interface Applications” section.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
Ground. Exposed pad must be connected to the same potential as the GND pin.
TRUTH TABLE
/RESET⁽¹⁾ S2 S1 S0 Outputs
1
0 X X Reference Clock (pass through)
1
1 0 0 Reference Clock ÷2
1
1 0 1 Reference Clock ÷4
1
1 1 0 Reference Clock ÷8
1
1 1 1 Reference Clock ÷16
0⁽¹⁾
X X X Q = LOW, /Q = HIGH
Clock Disable
Note 1. Reset/Disable function is asserted on the next clock input
(IN, /IN) high-to-low transition.
M9999-082407
[e-mail] or [phone]
2