MIC59P50YWM Datasheet, PDF (2/5 Pages) Micrel Semiconductor – 8-Bit Parallel-Input Protected Latched Driver

MIC59P50
Micrel
Absolute Maximum Ratings T_A = +25°C
Output Voltage (V_CE) .................................................... 80V
Supply Voltage (V_DD) .................................................... 15V
(V_DD – V_EE) ............................................................... 25V
Input Voltage (V_IN) ............................... –0.3V to V_DD+0.3V
Continuous Collector Current (I_C) ............................ 500mA
Protected Current ............................................ 1.5A, Note 1
Power Dissipation (P_D)
Plastic DIP (N) ......................................................... 2.4W
Derate above T_A = +25°C ............................ 24mW/°C
PLCC (V) ................................................................. 1.6W
Derate above T_A = +25°C ............................ 16mW/°C
Wide SOIC (WM) .................................................... 1.4W
Derate above T_A = +25°C ............................ 14mW/°C
Operating Temperature (T_A)
Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C
Storage Temperature (T_S) ....................... –65°C to +150°C
Junction Temperature (T_J) ...................................... +150°C
ESD ......................................................................... Note 2
Note 1:
Note 2:
Each channel. V_EE connection must be designed to minimize
inductance and resistance.
Devices are input-static protected but can be damage by
extremely high static charges.
PLCC Pin Configuration
43
2
1 28 27 26
IN 1 5
25 OUT 1
IN 2 6
IN 3 7
IN 4 8
MIC59P50BV
24 OUT 2
23 OUT 3
22 OUT 4
IN 5 ⁹
IN 6 10
21 OUT 5
20 OUT 6
IN 7 11
19 OUT 7
12 13 14 15 16 17 18
Allowable Output Current
MIC59P50BN
450
V _DD
Typical Input
IN
400
1 or 2
350
3
4
300
5
250
6
7
8
200
NUMBER OF OUTPUTS
150 _CONDUCTING
7
SIMULTANEOUSLY
100
0 10 20 30 40 50 60 70 80 90 100
PERCENT DUTY CYCLE
Pin Description
Pin
1
2
3
4–11
12
13
14–21
22
23
24
October 1998
Name
Description
FLAG
Error Flag. Open Collector Output is Low upon Overcurrent Fault or
Overtemperature Fault. OUTPUT ENABLE/RESET must be pulled high to
reset the flag and fault condition.
CLEAR
Sets All Latches OFF (open).
STROBE
Input Strobe Pin. Loads output latches when High.
INPUT
Parallel Inputs, 1 through 8
V_EE
Output Ground (Substrate). Most negative voltage in the system connects
here.
COMMON
Transient suppression diodes cathode common pin.
OUTPUT
Parallel Outputs, 8 through 1.
V_DD
OUTPUT ENABLE RESET
Logic Positive Supply voltage.
Output Enable Reset. When Low, Outputs are active. When High, outputs
are inactive and the Flag and outputs are reset from a fault condition. An
undervoltage condition emulates a high OE input.
V_SS
Logic reference (Ground) pin.
7-59