MIC261203ZA Datasheet, PDF (19/28 Pages) Micrel Semiconductor – 28V, 12A Hyper Speed Control Synchronous DC/DC Buck Regulator

Micrel, Inc.
The total output ripple is a combination of the ESR and
output capacitance. The total ripple is calculated in
Equation 10:
ΔV_OUT(pp) =
( ) _{}
C
ΔI_L(PP)
OUT ^{× f}SW
× 8 ^{2}
+
ΔI_L(PP) × ESR _COUT
2
Eq. 10
where:
D = duty cycle
C_OUT = output capacitance value
f_SW = switching frequency
As described in the “Theory of Operation” subsection in
Functional Description, the MIC261203-ZA requires at
least 20mV peak-to-peak ripple at the FB pin to make the
g_m amplifier and the error comparator behave properly.
Also, the output voltage ripple should be in phase with
the inductor current. Therefore, the output voltage ripple
caused by the output capacitors value should be much
smaller than the ripple caused by the output capacitor
ESR. If low-ESR capacitors, such as ceramic capacitors,
are selected as the output capacitors, a ripple injection
method should be applied to provide enough feedback
voltage ripple. Please refer to the “Ripple Injection”
subsection for more details.
The voltage rating of the capacitor should be twice the
output voltage for tantalum and 20% greater for
aluminum electrolytic or OS-CON. The output capacitor
RMS current is calculated in Equation 11.
I_{COUT (RMS)}
=
ΔI_L(PP)
12
The power dissipated in the output capacitor is:
Eq. 11
P_{DISS(COUT )}
=
I_COUT
2
(RMS)
× ESR _COUT
Eq. 12
Input Capacitor Selection
The input capacitor for the power stage input V_IN should
be selected for ripple current rating and voltage rating.
Tantalum input capacitors may fail when subjected to
high inrush currents which are caused by turning the
input supply on. A tantalum input capacitor’s voltage
rating should be at least two times the maximum input
voltage to maximize reliability. Aluminum electrolytic, OS-
CON, and multilayer polymer film capacitors can handle
the higher inrush currents without voltage derating. The
input voltage ripple primarily depends on the input
capacitor’s ESR. The peak input current is equal to the
peak inductor current, so:
∆V_IN = I_L(PK) × ESR _CIN
Eq. 13
MIC261203-ZA
The input capacitor must be rated for the input current
ripple. The RMS value of input capacitor current is
determined at the maximum output current. Assuming the
peak-to-peak inductor current ripple is low:
I_CIN(RMS) ≈ I_OUT(max) × D × (1− D)
The power dissipated in the input capacitor is:
Eq. 14
P_DISS(CIN) = I_CIN(RMS)2 × ESR_CIN
Eq. 15
Ripple Injection
The V_FB ripple required for proper operation of the
MIC261203-ZA g_m amplifier and error comparator is
20mV to 100mV. However, the output voltage ripple is
generally designed as 1% to 2% of the output voltage.
For a low output voltage, such as a 1V, the output voltage
ripple is only 10mV to 20mV, and the feedback voltage
ripple is less than 20mV. If the feedback voltage ripple is
so small that the g_m amplifier and error comparator can’t
sense it, then the MIC261203-ZA will lose control and the
output voltage is not regulated. In order to have some
amount of V_FB ripple, a ripple injection method is applied
for low output voltage ripple applications.
The applications are divided into three situations
according to the amount of the feedback voltage ripple:
1. Enough ripple at the feedback voltage caused by the
large ESR of the output capacitors.
As shown in Figure 5, the converter is stable without
any ripple injection. The feedback voltage ripple is:
R2
ΔV_FB(pp) = _{R1 + R2} × ESR _COUT × ΔI_{L (pp)}
Eq. 16
where ΔI_L(pp) is the peak-to-peak value of the inductor
current ripple.
2. Inadequate ripple at the feedback voltage caused by
the small ESR of the output capacitors.
The output voltage ripple is fed into the FB pin
through a feedforward capacitor C_ff in this situation,
as shown in Figure 6. The typical C_ff value is between
1nF and 100nF. With the feedforward capacitor, the
feedback voltage ripple is very close to the output
voltage ripple:
ΔV_FB(pp) ≈ ESR × ΔI_{L (pp)}
Eq. 17
3. Virtually no ripple at the FB pin voltage due to the
very-low ESR of the output capacitors.
June 11, 2013
19
Revision 1.0