KSZ8895MQ_12 Datasheet, PDF (19/116 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Pin Description (Continued)
Pin Number
100
Pin Name
VDDIO
Type⁽¹⁾
P
101
LED2-2
IPU/O
102
LED2-1
IPU/O
103
LED2-0
IPU/O
104
LED1-2
IPU/O
105
LED1-1
IPU/O
106
LED1-0
IPU/O
107
MDC
IPU
108
MDIO
IPU/O
109
SPIQ
IPU/O
110
SPIC/SCL
IPU/O
111
SSPID/SDA
IPU/O
112
SPIS_N
IPU
Port
2
2
2
1
1
1
All
All
All
All
All
All
Pin Function⁽²⁾
3.3V, 2.5V or 1.8V digital V_DD for digital I/O circuitry.
LED indicator 2.
Strap option for RQ only:
PU (default) = Select the device as clock mode in SW5- RMII,
25MHz crystal/oscillator to X1/X2 pins of the device and pins of
SMRXC and PMRXC output 50MHz clock.
PD = Select the device as normal mode in SW5-RMII. Switch
MAC5 used only. The input clock from X1/X2 pins is not used, the
device’s clock source comes from SMTXC/SMREFCLK pin which
the 50MHz reference clock comes from external 50MHz clock
source, PMRXC can output 50MHz clock for P5-RMII interface in
the normal mode.
LED indicator 1.
Strap option: for Port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register60 bit[7].
LED indicator 0.
LED indicator 2.
LED indicator 1.
Strap option: for port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register60 bit[4].
LED indicator 0.
Strap option for port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or
fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
Switch or PHY[5] MII management (MIIM registers) data clock. Or
SMI interface clock
Switch or PHY[5] MII management (MIIM registers) data I/O. Or
SMI interface data I/O.
Features internal pull down to define pin state when not driven.
Note: Need an external pull-up when driven.
SPI serial data output in SPI slave mode.
Note: Need an external pull-up when driven.
(1) Input clock up to 25MHz in SPI slave mode,
(2) output clock at 61kHz in I²C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
(1) Serial data input in SPI slave mode;
(2) serial data input/output in I²C master mode. See “Pin 113.”
Note: Need an external pull-up when driven.
Active low.
(1) SPI data transfer start in SPI slave mode. When SPIS_N is
high, the KSZ8895MQ/RQ/FMQ/RQ/FMQ is deselected and SPIQ
is held in high impedance state, a high-to-low transition to initiate
the SPI data transfer.
(2) not used in I²C master mode.
March 2012
19
M9999-032612-1.5