MIC2584_05 Datasheet, PDF (17/28 Pages) Micrel Semiconductor – Dual-Channel Hot Swap Controller/Sequencer

MIC2584/2585
The sequenced output feature is enabled for the MIC2585 by
placing a capacitor from CDLY to ground. The –1 option
allows for V_OUT2 to follow V_OUT1 and the –2 option allows for
V_OUT1 to follow V_OUT2 during start-up (See "Timing Dia-
grams, Figure 5"). The sequenced output delay time is
determined using the following equation:
t_DLY
≅ C_DLY
×
V_DELAY
I_DELAY
≅ 0.2 × C_DLY (µF)
(9)
where V_DELAY, the CDLY pin threshold, is typically 1.235V,
I_DELAY, the CDLY pin charge current, is typically 6µA, and
C_DLY is the capacitor connected to CDLY. Tables 2, 3, and 4
provide a quick reference for several timer calculations using
select standard value capacitors.
Undervoltage Lockout
Internal circuitry keeps both GATE output charge pumps off
until VCC1 and VCC2 exceed 2.165V and 0.8V, respectively.
C_POR
0.01µF
t_START
1.2ms
t_POR
5ms
0.033µF
4ms
16.5ms
0.05µF
6ms
25ms
0.1µF
12ms
50ms
0.33µF
40ms
165ms
0.47µF
56ms
235ms
1µF
120ms
500ms
Table 2. Selected Power-On Reset and
Start-Up Delays
Micrel
C_FILTER
220pF
t_OCSLOW
110µs
680pF
340µs
1000pF
500µs
3300pF
1.6ms
0.01µF
5ms
0.047µF
23.5ms
0.1µF
50ms
0.33µF
165ms
Table 3. Selected Overcurrent Timer Delays
C_DLY
4700pF
t_DLY
950µs
0.01µF
2ms
0.047µF
9.5ms
0.1µF
20ms
0.33µF
66ms
0.82µF
165ms
1µF
200ms
2.2µF
440ms
Table 4. Selected Sequenced Output Delays
March 2005
17
MIC2584/2585