MIC5165 Datasheet, PDF (16/24 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination

Micrel, Inc.
PCB Layout Guideline
Warning!!! To minimize EMI and output noise, follow
these layout recommendations.
PCB Layout is critical to achieve reliable, stable and
efficient performance. A ground plane is required to
control EMI and minimize the inductance in power,
signal and return paths.
The following guidelines should be followed to insure
proper operation of the MIC5165 controller application.
IC and MOSFET
• Place the IC close to the point of load (POL).
• The trace connecting controller drive pins to
MOSFETs gates should be short and wide to avoid
oscillations. These oscillations are the result of tank
circuit formed by trace inductance and gate
capacitance.
• Use fat traces to route the input and output power
lines.
• Signal and power grounds should be kept separate
and connected at only one location.
Input Capacitor
• Place the input capacitor next.
• Place the input capacitors on the same side of the
board and as close to the MOSFET and IC as
possible.
• Place a ceramic bypass capacitor next to MOSFET.
• Keep both the VIN and PGND connections short.
• Place several vias to the ground plane close to the
input capacitor ground terminal, but not between the
input capacitors and MOSFET.
MIC5165
• Use either X7R or X5R dielectric input capacitors.
Do not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
• If a Tantalum input capacitor is placed in parallel
with the input capacitor, it must be recommended for
switching regulator applications and the operating
voltage must be derated by 50%.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass capacitor must be used to limit the over-
voltage spike seen on the input supply with power is
suddenly applied.
Output Capacitor
• Use a wide trace to connect the output capacitor
ground terminal to the input capacitor ground
terminal.
• Phase margin will change as the output capacitor
value and ESR changes. Contact the factory if the
output capacitor is different from what is shown in
the BOM.
• The feedback trace should be separate from the
power trace and connected as close as possible to
the output capacitor. Sensing a long high current
load trace can degrade the DC load regulation.
June 2010
16
M9999-061510-B