MIC24053 Datasheet, PDF (16/30 Pages) Micrel Semiconductor – 12V, 9A High-Efficiency Buck Regulator

Micrel, Inc.
In each switching cycle of the MIC24053 converter, the
inductor current is sensed by monitoring the low-side
MOSFET in the OFF period. If the peak inductor current
is greater than 14A, the MIC24053 turns off the high-side
MOSFET and a soft-start sequence is triggered. This
mode of operation is called “hiccup mode.” Its purpose is
to protect the downstream load in case of a hard short.
The load current-limit threshold has a foldback
characteristic related to the feedback voltage as shown
in Figure 4.
Current Limit Threshold
vs. Feedback Voltage
20
16
12
8
4
0
0.0
0.2
0.4
0.6
0.8
1.0
FEEDBACK VOLTAGE (V)
Figure 4. MIC24053 Current-Limit Foldback Characteristic
Power Good (PG)
The Power Good (PG) pin is an open-drain output that
indicates logic high when the output is nominally 92% of
its steady-state voltage. A pull-up resistor of more than
10kΩ should be connected from PG to VDD.
MIC24053
MOSFET Gate Drive
The Block Diagram (Figure 1) shows a bootstrap circuit
consisting of D1 (a Schottky diode is recommended) and
C_BST. This circuit supplies energy to the high-side drive
circuit. Capacitor C_BST is charged, while the low-side
MOSFET is on, and the voltage on the SW pin is
approximately 0V. When the high-side MOSFET driver is
turned on, energy from C_BST is used to turn the MOSFET
on. As the high-side MOSFET turns on, the voltage on
the SW pin increases to approximately V_IN. Diode D1 is
reverse biased and C_BST floats high while continuing to
keep the high-side MOSFET on. The bias current of the
high-side driver is less than 10mA, so a 0.1μF to 1μF
capacitor is sufficient to hold the gate voltage with
minimal droop for the power stroke (high-side switching)
cycle; that is, ΔBST = 10mA x 1.67μs/0.1μF = 167mV.
When the low-side MOSFET is turned back on, C_BST is
recharged through D1. A small resistor (R_G), which is in
series with C_BST, can be used to slow down the turn-on
time of the high-side N-channel MOSFET.
The drive voltage is derived from the V_DD supply voltage.
The nominal low-side gate drive voltage is V_DD and the
nominal high-side gate drive voltage is approximately
V_DD – V_DIODE, where V_DIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side
and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both
MOSFETs.
November 2012
16
M9999-110712-A