KSZ8041TL Datasheet, PDF (16/58 Pages) Micrel Semiconductor – 10Base-T/100Base-TX/100Base-FX Physical Layer Transceiver

Micrel, Inc.
KSZ8041TL/FTL
Pin Number
23
Pin Name
DUPLEX
42
(KSZ8041TL)
NWAYEN
42
NWAYEN
(KSZ8041FTL)
Type⁽¹⁾
Ipu/O
Ipu/O
Ipu/O
Pin Function
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-
Negotiation.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE or PCS Loopback mode, or is not configured with an incorrect PHY Address.
April 2007
16
M9999-042707-1.1