SY89538L Datasheet, PDF (15/23 Pages) Micrel Semiconductor – 3.3V PRECISION LVPECL AND LVDS PROGRAMMABLE MULTIPLE OUTPUT BANK CLOCK SYNTHESIZER AND FANOUT BUFFER WITH ZERO DELAY

Micrel, Inc.
SY89538L
f_VCO (MHz)
Min.
Max.
2.35
3.02
2.35
3.02
2.35
3.02
2.35
3.02
Post-
Pre-
Divider Divider
1
2
1
3
1
4
1
5
f_OUT (MHz)
Min.
Max.
588.0 755.0
392.0 503.0
294.0 378.0
235.0 302.0
Ref-Divider = 1
f_REF (MHz)
Min.
Max.
588.0 755.0
392.0 503.0
294.0 378.0
235.0 302.0
Ref-Divider = 2
f_REF (MHz)
Min.
Max.
294.0 377.5
196.0 251.5
147.0 189.0
117.5 151.0
Ref-Divider = 4
f_REF (MHz)
Min.
Max.
147.0
188.8
98.0
125.8
73.5
94.5
58.8
75.5
Ref-Divider = 8
f_REF (MHz)
Min.
Max.
73.5
94.4
49.0
62.9
36.8
47.3
29.4
37.8
2.35
3.02
2
2.35
3.02
2
2.35
3.02
2
2.35
3.02
2
2
294.0 378.0 294.0 378.0 147.0 189.0
73.5
94.5
36.8
47.3
3
196.0 252.0 196.0 252.0 98.0 126.0
49.0
63.0
24.5
31.5
4
147.0 189.0 147.0 189.0 73.5
94.5
36.8
47.3
18.4
23.6
5
118.0 151.0 118.0 151.0 59.0
75.5
29.5
37.8
14.8
18.9
2.35
3.02
8
2.35
3.02
8
2.35
3.02
8
2.35
3.02
8
2
73.4
94.4
73.4
94.4
36.7
47.2
18.4
23.6
Not
11.8
Valid
3
49.0
62.9
49.0
62.9
24.5
31.5
12.3
15.7
Not
Not
Valid
Valid
4
36.7
47.2
36.7
47.2
18.4
23.6
Not
11.8
Not
Not
Valid
Valid
Valid
5
29.4
37.8
29.4
37.8
14.7
18.9
Not
Not
Not
Not
Valid
Valid
Valid
Valid
Table 9. Zero Delay Divider Cases
Considerations when in zero delay mode:
• The input and output frequency range is
29.375MHz to 756MHz
• The phase detector frequency range is
9.325MHz to 94.5MHz
• There are cases in which certain divider
combinations at certain frequencies are
not valid, see Table 9 for more details
• Systematic phase offset is caused by added
and parasitic capacitance
• Phase offset is introduced by increased trace
length
• Phase offset second order effects can be
introduced with high ε_R die-electric constants
since the velocity of electromagnetic waves
slows down as the die-electric constant
increases
October 2005
15
M9999-101105-B
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