MIC2358 Datasheet, PDF (14/29 Pages) Micrel Semiconductor – IEEE 802.3af Octal Power Sourcing Equipment Controller

Micrel, Inc.
The power budget may be managed across multiple
MIC2358YLQ devices by tying together the SPMBUS
pins of each device to a single budget-establishing
resistor.
To disable Shared Power Management tie the
SPMBUS pin-to-ground or disable SPM by the host.
Port Prioritization
The MIC2358YLQ offers Port Priority to enable
additional flexibility in managing the power budget.
In Managed Mode, the host software can assign each
port one of four levels of priority: critical, high,
medium, or low. During an emergency power supply
disruption event such as brown out, the host has the
flexibility to globally declare a minimum priority level
for a port to be powered following detection of a PD
and/or declare a minimum priority level for a port to
remain powered. Each individual port’s assigned
priority level is compared with global priority
declaration and if determined of a lower priority level
will then go to the POWER_DENIED state.
If multiple ports are assigned the same priority level
(higher than the minimum priority referred to above),
and the power supply is inadequate to power all of the
ports, then none of the ports will be powered normally.
Thus it is important to manage the priority levels for
the most important levels.
The Port Prioritization power management scheme is
complementary to Shared Power Management.
Supply Voltage Overvoltage and Undervoltage
Protection
The MIC2358YLQ monitors the input power supply for
overvoltage and undervoltage conditions. If the supply
voltage reaches VGOVP, all ports immediately shut
off and overvoltage fault status is reported to host by
the Global Status Register (0x45) bit 1, which may be
read by the host.
If the supply voltage drops off to VGUVP,
undervoltage fault status is reported to host by the
Global Status Register (0x45) bit 2, which may be
read by the host.
Digital Logic Power
The MIC2358YLQ must be supplied with 5V (VDD).
VDD supplies power for most of device internal analog
and all internal logic circuitry including SMBus
interface. All logic inputs and outputs reference to
DRTN. DRTN and ARTN are completely isolated
internally to the MIC2358YLQ.
July 2010
MIC2358YLQ
Non-Compliant IEEE 802.3af Features
For enhanced system flexibility, the MIC2358YLQ
supports non-compliant IEEE 802.3af or legacy PDs
detection resistance value. This would enable the
MIC2358YLQ to support pre-802.3af standard PD
Detection schemes. The host can program acceptable
lower threshold as low as 400Ω (dec 1x400) by the
Global_Detect_Min_Register (0x48) and higher
threshold as high as 102kΩ (dec 255x400) by the
Global_Detect_Max_Register
(0x49).
This
programming affects all ports and cannot be done per
port basis.
SMBus Serial Interface
The MIC2358YLQ communicates with a host (master)
using the standard 2-wire interface as described in the
SMBus Specification Version 2.0.
The SMBus is an extension of the I2C bus, and the
MIC2358YLQ is also compatible with the I2C bus
standard. The I2C interface allows easy application of
opto-coupler circuitry to maintain system isolation
when a ground based micro-controller host is
required. The MIC2358YLQ features separate input
and output data pins (SDAIN and SDAOUT) for use
with opto-couplers. For applications where opto-
isolation is not required, SDAIN and SDAOUT are tied
together.
The SMBus standard requires seven-bit device
addressing. The MIC2358YLQ top two most
significant address bits are hardwired to 10 with the
next five bits specified by strapping five pins on the
device.
The MIC2358YLQ uses standard Write_Byte and
Read_Byte, for communication with its host. The
Write_Byte operation (see Figure 1) involves sending
the device’s slave address (with the R/W bit low to
signal a write operation), followed by the address of
the register to be operated upon and the data byte.
The Read_Byte operation (see Figure 2) is a
composite write and read operation: the host first
sends the device’s slave address followed by the
register address, as in a write operation. A new start
bit must then be sent to the MIC2358YLQ, followed by
a repeat of the slave address with the R/W bit (LSB)
set to the high (read) state. The data to be read from
the part may then be clocked out.
The MIC2358YLQ expects to be interrogated using
the Alert Response Address once it has asserted its
interrupt output, /SMBINT. Following an interrupt, a
successful response to the A.R.A. or a read operation
on EVENT register will cause /SMBINT to be de-
asserted. EVENT will also be cleared by the read
operation. Reading EVENT following an interrupt is
an acceptable substitute for using the A.R.A., if the
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