SY89296U_11 Datasheet, PDF (13/17 Pages) Micrel Semiconductor – 2.5V/3.3V 1.5GHz Precision LVPECL Programmable Delay

Micrel, Inc.
Application Information
For best performance, use good high frequency layout
techniques, filter V_CC supplies, and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY89296U data inputs and outputs.
V_BB Reference
The VBB pin is an internally generated reference and is
available for use only by the SY89296U. When unused,
this pin should be left unconnected. The two common
uses for V_BB are to handle a single-ended PECL input,
and to re-bias inputs for AC-coupling applications.
If either IN or /IN is driven by a single-ended output, V_BB
is used to bias the unused input. Please refer to Figure
10. The PECL signal driving the SY89296U may
optionally be inverted in this case.
When the signal is AC-coupled, V_BB is used, as shown in
Figure 13, to re-bias IN and/or /IN. This ensures that
SY89296U inputs are within acceptable common mode
range.
In all cases, V_BB current sinking or sourcing must be
limited to 0.5mA or less.
SY89296U
Setting D Input Logic Thresholds
In all designs where the SY89296U GND supply is at
zero volts, the D inputs can accommodate CMOS and
TTL level signals, as well as PECL or LVPECL. Figures
11, 12, and 14 show how to connect VCF and VEF for all
possible cases.
Cascading
Two or more SY89296U may be cascaded in order to
extend the range of delays permitted. Each additional
SY89296U adds about 3.2ns to the minimum delay and
adds another 10240ps to the delay range.
Internal cascade circuitry has been included in the
SY89296U. Using this internal circuitry, the SY89296U
may be cascaded without any external gating.
Examples of cascading 2, 3, or 4 SY89296U appear in
Figures 7, 8, and 9.
November 2011
13
M9999-112211
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