KSZ9692MPB Datasheet, PDF (13/44 Pages) Micrel Semiconductor – Integrated Gigabit Networking and Communications Controller

Micrel, Inc.
KSZ9692MPB/KSZ9692XPB
Figure 7. 16-bit NAND Interface Examples
DDR Controller
The KSZ9692MPB/KSZ9692XPB DDR memory controller provides interface for accessing external Double Data Rate
Synchronous DRAM. In addition, the KSZ9692MPB/KSZ9692XPB provides two integrated DDR differential clock drivers
for a complete glueless DDR interface solution.
• Up to 200 MHz clock frequency (400 MHz data rate)
• Supports one 32-bit data width bank (16-bit optional)
• Up to 128 MB of addressable space is available with 12 columns and 14 row address lines
• Supports all DDR device densities up to 1Gb
• Supports all DDR device data width x8 and x16
• Configurable DDR RAS and CAS timing parameters
• Two integrated JEDEC Specification JESD82-1 compliant differential clock drivers for a glueless DDR interface solution
• JEDEC Specification SSTL_2 I/Os
March 2010
13
M9999-031810-4.0