MIC5166 Datasheet, PDF (12/25 Pages) Micrel Semiconductor – 3A High-Speed Low VIN DDR Terminator

Micrel, Inc.
Application Information
DDR memory requires two power supplies, one for the
memory chip, referred to as V_DDQ and the other for a
termination supply V_TT, which is one-half V_DDQ. With
memory speeds in excess of 300MHz, the memory
system bus must be treated as a transmission line. To
maintain good signal integrity the memory bus must be
terminated to minimize signal reflections. Figure 2 shows
the simplified termination circuit. Each control, address
and data lines have these termination resistors RS and
RT connected to them.
Figure 2. DDR Memory Termination Circuit
Bus termination provides a means to increase signaling
speed while maintaining good signal integrity. The
termination network consists of a series resistor (R_S) and
a terminating resistor (R_T). Values of R_S range between
10Ω to 30Ω with a typical of 22Ω, while R_T ranges from
22Ω to 28Ω with a typical value of 25Ω. V_REF must
maintain half V_DDQ with a ±1% tolerance, while V_TT will
dynamically sink and source current to maintain a
termination voltage of ±40mV from the V_REF line under all
conditions. This method of bus termination reduces
common-mode noise, settling time, voltage swings,
EMI/RFI and improves slew rates.
V_DDQ powers all the memory ICs, memory drivers and
receivers for all the memory bits in the DDR memory
system. The MIC5166 regulates V_TT to V_DDQ/2 during
sourcing or sinking current.
MIC5166
The memory bits are not usually all at a logic high or
logic low at the same time so the V_TT supply is usually
not sinking or sourcing −3A or +3A current continuously.
V_TT
V_TT is regulated to V_REF. Due to high-speed signaling, the
load current seen by V_TT is constantly changing. To
maintain adequate transient response, two 10µF ceramic
capacitors are required. The proper placement of
ceramic capacitors is important to reduce both ESR and
ESL such that high-current and high-speed transients do
not exceed the dynamic voltage tolerance requirement of
V_TT. The ceramic capacitors provide current during the
fast edges of the bus transition. Using several smaller
ceramic capacitors distributed near the termination
resistors is important to reduce the effects of PCB trace
inductance.
V_DDQ
The V_DDQ input on the MIC5166 is used to create the
internal reference voltage for V_TT. The reference voltage
is generated from an internal resistor divider network of
two 500kΩ resistors, generating a reference voltage V_REF
that is V_DDQ/2. The V_DDQ input should be Kelvin
connected as close as possible to the memory supply
voltage.
Since the reference is simply V_DDQ/2, any perturbations
on V_DDQ will also appear at half the amplitude on the
reference. For this reason a 4.7µF ceramic capacitor is
required on the V_DDQ supply. This will aid performance
by improving the source impedance over a wide
frequency range.
Sense
The sense (SNS) pin provides the path for the error
amplifier to regulate V_TT. The SNS input must also be
Kelvin connected to the V_TT bypass capacitors. If the
SNS input is connected to close to the MIC5166, the IR
drop of the PCB trace can cause the V_TT voltage at the
memory chip to be too low. Placing the MIC5166 as
close as possible to the DDR memory will improve the
load regulation performance.
Enable
The MIC5166 features an active-high enable input (EN)
that allows on-off control of the regulator. The current
through the device reduces to near “zero” when the
device is shutdown, with only <0.2µA of leakage current.
The EN input may be directly tied to V_BIAS. The active
high enable pin uses CMOS technology and the enable
pin cannot be left floating; a floating enable pin may
cause an indeterminate state on the output.
June 2012
12
M9999-060612-A