MIC4682_07 Datasheet, PDF (12/15 Pages) Micrel Semiconductor – Precision Current Limit SOIC-8 SuperSwitcher™ Buck Regulator

Micrel, Inc.
MIC4682
P_D
=
P_OUT
η
− P_OUT
P_D
=
5W _{− 5W}
0.81
P_D = 1.17W
A worst-case rule of thumb is to assume that 80% of the
total output power dissipation is in the MIC4682 (P_D(IC))
and 20%is in the diode-inductor-capacitor circuit.
P_D(IC) = 0.8 P_D
P_D(IC) = 0.8 × 1.17W
P_D(IC) = 0.936W
Calculate the worst-case junction temperature:
T_J = P _D(IC) θ_JC + (T_C – T_A) + T_A(max)
where:
T_J = MIC4682 junction temperature
P_D(IC) = MIC4682 power dissipation
θ_JC = junction-to-case thermal resistance.
The θ_JC for the MIC4682’s power-SOIC-8 is
approximately 20°C/W.
T_C = “pin” temperature measurement taken at
the entry point of pins 6 or 7.
T_A = ambient temperature
T_A(max) = maximum ambient
temperature for the specific design.
operating
Calculating the maximum junction temperature given a
maximum ambient temperature of 65°C:
T_J = 0.936 × 20°C/W + (45°C – 25°C) + 65°C
T_J = 103.7°C
This value is within the allowable maximum operating
junction temperature of 125°C as listed in “Operating
Ratings.” Typical thermal shutdown is 160°C and is
listed in “Electrical Characteristics.”
Layout Considerations
Layout is very important when designing any switching
regulator. Rapidly changing currents through the printed
circuit board traces and stray inductance can generate
voltage transients which can cause problems.
To minimize stray inductance and ground loops, keep
trace lengths, indicated by the heavy lines in Figure 4, as
short as possible. For example, D1 should be close to
pin 7 and pin 8. C_IN should be close to pin 5 and pin 6.
See “Applications Information: Thermal Considerations”
for ground plane layout.
The feedback pin should be kept as far way from the
switching elements (usually L1 and D1) as possible.
A circuit with sample layouts are provided. See Figures
5a though 5e. Gerber files are available upon request.
V_IN
+4V to +34V
C_IN
Power
SOIC-8
MIC4682BM
5 _IN
SW ⁸
4 _SHDN
FB ¹
GND I_SET
267 3
L1
68µH
D1
V_OUT
C_OUT R1
R2
GND
Figure 4. Critical Traces for Layout
J1
V_IN
4V to 34V
C1
10µF
50V
J2
GND
C2
10µF
50V
C3
0.1µF
50V
1 _{JP1 1-2=OFF}
JP1 2-3-ON
OFF
2
ON _JP1
3
R9
10M
U1 MIC4682BM
5 _IN
SW ⁸
1
4 _SHDN
3 _ISET
GND ⁷
2
FB ¹
R8
R7
R6
option 16.2k 25k
2 _JP3c 4 _JP3b6 _JP3a
2.0A 1.0A 0.6A
1
3
5
GND GND
2
6
L1
68µH
1
2
D1
B340A _R1
3.01k
C4
Option
R5
R4
6.49k 2.94k
R3
1.78k
2 _JP2a4 _JP2b 6 _JP2c 8
1.8V 2.5V 3.3V
1
3
5
7
R2
976
JP2d
5.0V
C5
220µF
10V
C6
Option
J3
V_OUT
C7
0.1µF
50V
J4
GND
Figure 5a. Evaluation Board Schematic Diagram
June 2007
12
M9999-061507