MIC384_05 Datasheet, PDF(12/22 Page) Micrel Semiconductor

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MIC384_05 Datasheet, PDF (12/22 Pages) Micrel Semiconductor – Three-Zone Thermal Supervisor

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MIC384

shutdown mode, and the interrupt status will not be retained.

Since entering shutdown mode stops A/D conversions, the

MIC384 is incapable of detecting or reporting temperature

events of any kind while in shutdown. Diode faults require

one or more A/D conversion cycles to be recognized, and

therefore will not be reported either while the device is in

shutdown (see "Diode Faults" above).

Fault_Queue

Fault queues (programmable digital ï¬lters) are provided

in the MIC384 to prevent false tripping due to thermal or

electrical noise. The two bits in CONFIG[4:3] set the depth

of Fault_Queue. Fault_Queue then determines the number

of consecutive temperature events (TEMPx > T_SETx,

or TEMPx < T_HYSTx) which must occur in order for the

condition to be considered valid. There are separate fault

queues for each zone. As an example, assume the part is

in comparator mode, and CONFIG[4:3] is programmed with

10b. The measured temperature in zone one would have to

exceed T_SET1 for four consecutive A/D conversions before

/INT would be asserted or the S1 status bit set. Similarly,

TEMP1 would then have to be less than T_HYST1 for four

consecutive conversions before /INT would be reset. Like

any ï¬lter, the fault queue function also has the effect of de-

laying the detection of temperature events. In this example,

it would take 4 x tCONV to detect a temperature event. The

depth of Fault_Queue vs. D[4:3] of the conï¬guration register

is shown in Table 4.

C ONFIG[4:3]

* Default s etting

F ault_Queue Depth

1 convers ion*

2 convers ions

4 convers ions

6 convers ions

Table 4. Fault_Queue Depth Settings

Interrupt Generation

Assuming the MIC384 is in interrupt mode and interrupts

are enabled, there are seven different conditions that will

cause the MIC384 to set one of the status bits, S0, S1, or

Micrel

S2, in CONFIG and assert its /INT output. These conditions

are listed in Table 5. When a temperature event occurs, the

corresponding status bit will be set in CONFIG. This action

cannot be masked. However, a temperature event will only

generate an interrupt signal on /INT if it is speciï¬cally enabled

by the interrupt mask bit (IM =0 in CONFIG). Following an

interrupt, the host should read the contents of the conï¬gura-

tion register to conï¬rm that the MIC384 was the source of the

interrupt. A read operation on any register will cause /INT to

be de-asserted. This is shown in Figure 5. The status bits

will only be cleared once CONFIG has been read.

Since temperature-to-digital conversions continue while /INT

is asserted, the measured temperature could change between

the MIC384âs assertion of /INT and the hostâs response. It

is good practice for the interrupt service routine to read the

value in TEMPx, to verify that the over-temperature or under-

temperature condition still exists. In addition, more than one

temperature event may have occurred simultaneously or in

rapid succession between the assertion of /INT and servic-

ing of the MIC384 by the host. The interrupt service routine

should allow for this eventuality. Keep in mind that clearing

the status bits and deasserting /INT is not sufï¬cient to allow

further interrupts to occur. TEMPx must become less than

T_HYSTx if the last event was an over-temperature condition,

or greater than T_SETx if the last event was an under-tem-

perature condition, before /INT can be asserted again.

Putting the device into shutdown mode will de-assert /INT

and clear the status bits (S0, S1, and S2). This should not

be done before completing the appropriate interrupt service

routine(s).

Polling

The MIC384 may either be polled by the host, or request the

hostâs attention via the /INT pin. In the case of polled opera-

tion, the host periodically reads the contents of CONFIG to

check the state of the status bits. The act of reading CON-

FIG clears the status bits. If more than one event that sets

a given status bit occurs before the host polls the MIC384,

only the fact that at least one such event has occurred will be

apparent to the host. For polled systems, the interrupt mask

bit should be set (IM = 1). This will disable interrupts from the

MIC384 and prevent the /INT pin from sinking current.

MIC384

September 2005

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