MIC2586 Datasheet, PDF (12/17 Pages) Micrel Semiconductor – Single-Channel, Positive High-Voltage Hot Swap Controller/Sequencer

Micrel
MIC2586/MIC2586R
removed/cycled, or c) the ON pin is toggled LOW then HIGH.
The duty cycle of the auto-restart function is therefore fixed
at 5% and the period of the auto-restart cycle is given by:
t _{AUTO_RESTA RT} = 20 × t_{FLT_AUTO}
( ) ( ) _{tAUTO-RESTART}
= 20 ×
C_TIMER
× V_TIMERH − V_TIMERL
I_TIMERUP
t _AUTO-RESTART
=
C_TIMER
× _{⎜⎜⎝⎛}250
ms
µF
⎟⎟⎠⎞
(7)
The auto-restart period for the example above where the
worse-case C_TIMER was calculated to be 3.3µF is:
t_AUTO-RESTART = 825ms
Input Undervoltage Lockout
The MIC2586/MIC2586R have an internal undervoltage
lockout circuit that inhibits operation of the controller’s
internal circuitry unless the power supply voltage is stable
and within an acceptable tolerance. If the supply voltage to
the controller with respect to ground is greater than the V_UVH
threshold voltage (8V typical), the controller’s internal circuits
are enabled and the controller is then ready for normal
operation pending the state of the ON pin voltage. Once in
steady-state operation, the controller’s internal circuits
remain active so long as the supply voltage with respect to
ground is higher than the controller’s internal V_UVL threshold
voltage (7.5V typical).
Power-is-Good Output Signals
For the MIC2586-1/MIC2586R-1, power-good output signal
PWRGD1 will be high impedance when the FB pin voltage is
higher than the V_FBH threshold and will pull down to GND
when the FB pin voltage is lower than the V_FBL threshold. For
the MIC2586-2/MIC2586R-2, power-good output signal
/PWRGD1 will pull down to GND when the FB pin voltage is
higher than the V_FBH threshold and will be high impedance
when the FB pin voltage is lower than the V_FBL threshold.
Hence, the (-1) parts have an active-HIGH PWRGDx signal
and the (-2) parts have an active-LOW /PWRGDx output.
PWRGDx (or /PWRGDx) may be used as an enable signal
for one or more DC/DC converter modules or for other
system functions. When used as an enable signal, the time
necessary for the PWRGDx (or /PWRGDx) signal to pull-up
(when in high impedance state) will depend upon the (RC)
load at the respective Power-is-Good pin.
Power-is-Good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) are asserted after the assertion of
PWRGD1 (/PWRGD1) by a user-programmable time delay
set by an external capacitor (C_PG) from the controller's
PGTIMER pin (Pin 7) to GND. An expression for the time
delay to assert PWRGD2 (or /PWRGD2) after PWRGD1 (or
/PWRGD1) asserts is given by:
t_{PG(1− 2)}
=
C_PG
I_CPG
× V_PG2
where V_PG2 (0.625V, typically) is the PWRGD2 (or
/PWRGD2) threshold voltage for PGTIMER and I_CPG (7µA,
typically) is the internal PGTIMER pin charging current.
Similarly, an expression for the time delay to assert
PWRGD3 (or /PWRGD3) after PWRGD1 (or /PWRGD1)
asserts is given by:
t_{PG(1− 3)}
=
C_PG
I_CPG
× V_PG3
where V_PG3 (1.25V, typically) is the PWRGD3 (or /PWRGD3)
threshold voltage for PGTIMER. Therefore, PWRGD2 (or
/PWRGD2) will be delayed after the assertion of PWRGD1
(or /PWRGD1) by:
t_PG(1−2)(ms) ≅ 90 × C_PG (µF)
(8)
PWRGD3 (/PWRGD3) follows the assertion of PWRGD1
(/PWRGD1) by a delay:
t_PG(1−3) (ms) ≅ 180 × C_PG (µF)
(9)
For example, for a C_PG of 0.1µF, PWRGD2 (or /PWRGD2)
will be asserted 9ms after PWRGD1 (or /PWRGD1).
PWRGD3 (or /PWRGD3) will then be asserted 9ms after
PWRGD2 (or /PWRGD2) and 18ms after the assertion of
PWRGD1 (or /PWRGD1). The relationships between V_OUT,
V_FBH, PWRGD1, PWRGD2, and PWRGD3 are shown in
Figures 5 and 6.
Each Power-is-Good output pin is connected to an open-
drain, N-channel transistor implemented with high-voltage
structures. These transistors are capable of operating with
pull-up resistors to supply voltages as high as 100V.
October 2004
12
M9999-102204
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