MIC23156 Datasheet, PDF (12/22 Pages) Micrel Semiconductor – 1.5A, 3MHz Synchronous Buck Regulator with HyperLight Load® and I2C Control for Dynamic Voltage Scaling

Micrel, Inc.
Functional Description
PVIN
The input supply (PVIN) provides power to the internal
MOSFETs for the switch mode regulator section. The
PVIN operating range is 2.7V to 5.5V so an input
capacitor with a minimum voltage rating of 6.3V is
recommended. Due to the high switching speed, a
minimum 2.2µF bypass capacitor placed close to PVIN
and the power ground (PGND) pin is required. Refer to
PCB Layout Recommendations (MLF Package) for more
details.
AVIN
Analog VIN (AVIN) provides power to the internal control
and analog supply circuitry. AVIN must be tied to PVIN
through a 10Ω RC filter. Careful layout should be
considered to ensure that any high-frequency switching
noise caused by PVIN is reduced before reaching AVIN.
A 2.2µF capacitor as close to AVIN as possible is
recommended. Refer to PCB Layout Recommendations
(MLF Package) for more details.
EN
A logic high signal on the enable pin activates the output
voltage of the device. A logic low signal on the enable pin
deactivates the output and reduces supply current to
0.1µA. Do not leave the EN pin floating. MIC23156
features external soft-start circuitry via the soft start (SS)
pin that reduces in-rush current and prevents the output
voltage from overshooting when EN is driven logic high.
Do not leave the EN pin floating.
SW
The switch (SW) connects directly to one end of the
inductor and provides the current path during switching
cycles. The other end of the inductor is connected to the
SNS pin, output capacitor and the load. Due to the high
speed switching on this pin, the switch node should be
routed away from sensitive nodes whenever possible.
SNS
The sense (SNS) pin is connected to the output of the
device to provide feedback to the control circuitry. The
SNS connection should be placed close to the output
capacitor. Refer to PCB Layout Recommendations (MLF
Package) for more details.
AGND
The analog ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the
signal ground should be separate from the power ground
MIC23156
(PGND) loop. Refer to PCB Layout Recommendations
(MLF Package) for more details.
PGND
The power ground (PGND) pin is the ground path for the
high current in PWM mode. The current loop for the
power ground should be as small as possible and
separate from the analog ground (AGND) loop as
applicable. Refer to PCB Layout Recommendations (MLF
Package) for more details.
PGOOD
The power good (PGOOD) pin is an open drain output
which indicates logic high when the output voltage is
typically above 90% of its steady state voltage. A pull-up
resistor of more than 5kΩ should be connected from
PGOOD to VOUT.
SS
The soft-start (SS) pin is used to control the output
voltage ramp up time. The approximate equation for the
ramp time in seconds is 820 × 103 × ln(10) × C_SS. For
example, for a C_SS = 120pF, T_RISE ≈ 230µs. Refer to the
“V_OUT Rise Time vs. C^SS” graph in the Typical
Characteristics section. The minimum recommended
value for C_SS is 120pF.
VI2C
Power connection for I²C bus voltage. Connect this pin to
the voltage domain of the I²C bus supply.
VSEL
Selectable output voltage of either of two I2C voltage
registers. A logic low selects buck register 1 and logic
high selects buck register 2. If no I²C programming is
used the output voltages will be as per the default voltage
register values. Do not leave floating.
SCL
The I²C clock input pin provides a reference clock for
clocking in the data signal. This is a fast-mode plus 1MHz
input pin, and requires a 4.7KΩ pull-up resistor.
SDA
The I²C data input/output pin allows for data to be written
to and read from the MIC23156. This is a fast-mode plus
1MHz I²C pin, and requires a 4.7KΩ pull-up resistor.
April 22, 2013
12
Revision 1.0