MIC2174 Datasheet, PDF (12/24 Pages) Micrel Semiconductor – 300kHz, Synchronous Buck Controller 300kHz, Synchronous Buck Controller

Micrel, Inc.
current and that there is a blanking delay of
approximately 150ns.
I_CL
= ^130mV
R_DS(ON)
+
V_OUT × T_DLY
L
−
ΔI_L(pp)
2
(3)
ΔI_L(pp)
=
V_OUT × (1− D)
f _SW×L
(4)
where:
V_OUT = The output voltage
T_DLY = Current limit blanking time, 150ns typical
ΔI_L(pp) = Inductor current ripple peak-to-peak value
D = Duty Cycle
f_SW = Switching frequency
The MOSFET R_DS(ON) varies 30% to 40% with
temperature; therefore, it is recommended to add a 50%
margin to I_CL in the above equation to avoid false current
limiting due to increased MOSFET junction temperature
rise. It is also recommended to connect LX pin directly to
the drain of the low-side MOSFET to accurately sense
the MOSFETs R_DS(ON).
MIC2174
MOSFET Gate Drive
The MIC2174 high-side drive circuit is designed to
switch an N-Channel MOSFET. The Block Diagram of
Figure 1 shows a bootstrap circuit, consisting of D1 (a
Schottky diode is recommended) and C_BST. This circuit
supplies energy to the high-side drive circuit. Capacitor
C_BST is charged, while the low-side MOSFET is on, and
the voltage on the LX pin is approximately 0V. When the
high-side MOSFET driver is turned on, energy from C_BST
is used to turn the MOSFET on. As the high-side
MOSFET turns on, the voltage on the LX pin increases
to approximately V_HSD. Diode D1 is reversed biased and
C_BST floats high while continuing to keep the high-side
MOSFET on. The bias current of the high-side driver is
less than 10mA so a 0.1μF to 1μF is sufficient to hold
the gate voltage with minimal droop for the power stroke
(high-side switching) cycle, i.e. ΔBST = 10mA x
3.33μs/0.1μF = 333mV. When the low-side MOSFET is
turned back on, C_BST is recharged through D1. A small
resistor R_G, which is in series with C_BST, can slow down
the turn-on time of the high-side N-channel MOSFET.
The drive voltage is derived from the supply voltage VIN.
The nominal low-side gate drive voltage is V_IN and the
nominal high-side gate drive voltage is approximately V_IN
– V_DIODE, where V_DIODE is the voltage drop across D1. An
approximate 30ns delay between the high-side and low-
side driver transitions is used to prevent current from
simultaneously flowing unimpeded through both
MOSFETs.
September 2009
12
M9999-090409-B