MIC74_06 Datasheet, PDF (11/18 Pages) Micrel Semiconductor – 2-Wire Serial I/O Expander and Fan Controller

Micrel, Inc.
Application Information
Bit Transfer
The data received on the DATA pin must be stable
during the high period of the clock.
DATA
CLK
Data Stable,
Data Valid
Data Change Allowed
Figure 3. Acceptable Bit Transfer Conditions
Data can change state only when the CLK line is low.
Refer to Figure 3.
Start and Stop Conditions
Two unique bus situations define “start” and “stop”
conditions. A high-to-low transition of the DATA line
while CLK is high indicates a start condition. A low-to-
high transition of the DATA line while CLK is high
defines a stop condition. See Figure 4.
DATA
MIC74
CLK
Start
StoP
Figure 4. Start and Stop Definitions
Start (S) and stop (P) conditions are always generated
by the bus master (host). After a start condition, the bus
is considered to be busy. The bus becomes free again
after a certain time following a stop condition or after
both CLK and DATA lines remain high for more than
50µs.
Serial Byte Format
Every byte consists of 8 bits. Each byte transferred on
the bus must be followed by an acknowledge bit. Bytes
are transferred with the MSB (most significant bit) first.
See Figure 5.
MSB
LSB
DATA
CLK
Start
123456789
123456789
ACK
Byte Complete
Figure 5. Serial Byte Format
ACK
StoP
Acknowledge and Not Acknowledge
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high)
during the acknowledge clock cycle.
In order to acknowledge (ACK) a byte, the receiver must
pull the DATA line low during the high period of the clock
pulse according the bus timing specifications. A slave
device that wishes to not acknowledge a byte must let
the DATA line remain high during the acknowledge clock
pulse. See Figure 6.
DATA
(Host)
MSB
LSB
NAK (high)
DATA
(Slave MIC74)
CLK
1 2 3 4 5 6 7 8 9 _{ACK (low)}
ACK
Figure 6. Acknowledge and Not Acknowledge
October 2006
11
M9999-101006