MIC2589 Datasheet, PDF (11/17 Pages) Micrel Semiconductor – SINGLE-CHANNEL NEGATIVE HIGH VOLTAGE HOT SWAP POWER CONTROLLERS/SEQUENCERS

MIC2589/2595
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying live
supply voltages (“hot swapped”), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit board’s supply pins. These current spikes
can cause the system’s supply voltages to temporarily go out
of regulation causing data loss or system lock-up. In more
extreme cases, the transients occurring during a hot swap
event may cause permanent damage to connectors or on-
board components.
The MIC2589 and the MIC2595 are designed to address
these issues by limiting the maximum current, which is
allowed to flow during hot swap events. This is achieved by
implementing a constant-current loop at turn-on. In addition
to inrush current control, the MIC2589 and the MIC2595
incorporate input voltage supervisory functions and user-
programmable overcurrent protection, thereby providing ro-
bust protection for both the system and the circuit board.
Start-Up Cycle
When the input voltage is to the IC is between the overvoltage
and undervoltage thresholds (MIC2589 and MIC2589R) or is
greater than V_ON (MIC2595 and MIC2595R), a start cycle is
initiated. When the IC is enabled, the GATE pin voltage rises
from 0V with respect to V_EE to approximately 10V above V_EE.
This 10V gate drive is sufficient to fully enhance commonly
available power MOSFETs for the lowest possible DC losses.
Capacitor C_GATE compensates circuitry internal to the IC,
while R4 minimizes the potential for high frequency parasitic
oscillations from occurring in M1. The drain current of the
MOSFET is regulated to ensure that it never exceeds the
programmed threshold, as described in the “Circuit Breaker
Function” section.
Capacitor C_FILTER sets the value of overcurrent detector
delay, t_FLT, which is the time for which an overcurrent event
must last to signal a fault condition and to cause an output
latch-off. These devices will be driving a capacitive load in
most applications, so a properly chosen value of C_FILTER
prevents false-, or nuisance-, tripping at turn-on as well as
providing immunity to noise spikes after the start-up cycle is
complete. The procedure for selecting a value for C_FILTER is
given in the “Circuit Breaker Function” section.
Resistor R4, in series with the power MOSFET’s gate, may be
required in some layouts to minimize the potential for para-
sitic oscillations occurring in M1. Note though, that resistance
in this device of the circuit has a slight destabilizing effect
upon the MIC2589/95’s current regulation loop. If possible,
use high-frequency PCB layout techniques and use a dummy
resistor, such that R4 = 0Ω. If during prototyping an R4 is
required, common values for R4 range between 4.7Ω to 20Ω
for various power MOSFETs.
Micrel
The Power-Good Output Signals
For the MIC2589/95-1 and MIC2589R/95R-1, power-good
output signal PWRGD1 will be high impedance when V_DRAIN
drops below V_PGTH, and will pull-down to V_DRAIN when
V_DRAIN is above V_PGTH. For the MIC2589/95-2 and the
MIC2589R/95R-2, power-good output signal /PWRGD1 will
pull down to the potential of the V_DRAIN pin when V_DRAIN
drops below V_PGTH and will be high impedance when V_DRAIN
is above V_PGTH. Hence, the -1 parts have an active-high
PWRGD_X signal and the -2 parts have an active-low /PWRGD_X
output. PWRGD_X (or /PWRGD_X) may be used as an enable
signal for one or more following DC/DC converter modules or
for other system uses as desired. When used as an enable
signal, the time necessary for the PWRGD (or /PWRGD)
signal to pull-up (when in high impedance state) will depend
upon the load (RC) that is present on this output.
Power-good output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) follow the assertion of PWRGD1
(/PWRGD1) with a sequencing delay set by an external
capacitor (C_PG) from the controller’s PGTIMER pin (Pin 2) to
V_EE. An expression for the sequencing delay between
PWRGD2 and PWRGD1 is given by:
t_{PGDLY2−1}
=
V_THRESH(PG2) ×
I_PGTIMER
C_PG
where V_THRESH(PG2) (= 0.63V, typically) is the PWRGD2
threshold voltage for PGTIMER and I_PGTIMER (= 45µA, typi-
cally) is the internal PGTIMER charge current. Similarly, an
expression for the sequencing delay between PWRGD3 and
PWRGD2 is given by:
( ) _{tPGDLY3−2 =}
V_THRESH(PG3) – V_THRESH(PG2)
I_PGTIMER
× C_PG
where V_THRESH(PG3) (= 1.15V, typically) is the PWRGD3
threshold voltage for PGTIMER. Therefore, power-good out-
put signal PWRGD2 (/PWRGD2) will be delayed after the
assertion of PWRGD1 (/PWRGD1) by:
t_PGDLY2-1 (ms) ≅ 14 × C_PG(µF) ms
Power-good output signal PWRGD3 (/PWRGD3) follows the
assertion of PWRGD2 by a delay:
t_PGDLY3-2 (ms) ≅ 11.5 × C_PG(µF) ms
For example, for a 10µF value for C_PG, power-good output
signal PWRGD2 will be asserted 140ms after PWRGD1.
Power-good signal PWRGD3 will then be asserted 140ms
after PWRGD2 and 255ms after the assertion of PWRGD1.
The relationships between V_DRAIN, V_PGTH, PWRGD1,
PWRGD2, and PWRGD3 are shown in Figure 6.
March 2004
11
M9999-031504