MIC23303 Datasheet, PDF (11/21 Pages) Micrel Semiconductor – 4MHz PWM 3A Buck Regulator with HyperLight Load™ and Power Good

Micrel, Inc.
MIC23303
Functional Description
PVIN
The input supply (PVIN) provides power to the internal
MOSFETs for the switch mode regulator section. The VIN
operating range is 2.7V to 5.5V so an input capacitor, with
a minimum voltage rating of 6.3V, is recommended. Due to
the high switching speed, a minimum 4.7µF bypass
capacitor placed close to PVIN and the power ground
(PGND) pin is required. Refer to the PCB Layout
Recommendations for details.
AVIN
Analog VIN (AVIN) provides power to the internal control
and analog supply circuitry. AVIN and PVIN must be tied
together. Careful layout should be considered to ensure
high frequency switching noise caused by PVIN is reduced
before reaching AVIN. A 1µF capacitor as close to AVIN
as possible is recommended. See PCB Layout
Recommendations for details.
EN
A logic high signal on the enable pin activates the output
voltage of the device. A logic low signal on the enable pin
deactivates the output and reduces supply current to
nominal 0.01µA. MIC23303 features external soft-start
circuitry via the soft start (SS) pin that reduces in-rush
current and prevents the output voltage from overshooting
when EN is driven logic high. Do not leave the EN pin
floating.
SW
The switch (SW) connects directly to one end of the
inductor and provides the current path during switching
cycles. The other end of the inductor is connected to the
load, SNS pin, and output capacitor. Due to the high speed
switching on this pin, the switch node should be routed
away from sensitive nodes whenever possible.
SNS
The sense (SNS) pin is connected to the output of the
device to provide feedback to the control circuitry. The
SNS connection should be placed close to the output
capacitor. Refer to the PCB Layout Recommendations for
more details.
AGND
The analog ground (AGND) is the ground path for the
biasing and control circuitry. The current loop for the signal
ground should be separate from the power ground (PGND)
loop. Refer to the PCB Layout Recommendations for more
details.
PGND
The power ground pin is the ground path for the high
current in PWM mode. The current loop for the power
ground should be as small as possible and separate from
the analog ground (AGND) loop as applicable. Refer to the
PCB Layout Recommendations for more details.
PG
The power good (PG) pin is an open-drain output that
indicates logic high when the output voltage is typically
above 90% of its steady state voltage. A pull-up resistor of
more than 5kΩ should be connected from PG to V_OUT.
SS
The soft start (SS) pin is used to control the output voltage
ramp-up time. The approximate equation for the ramp time
in seconds is 250 × 10³ × ln(10) × C_SS.
For example, for C_SS = 2.2nF, T_rise ~ 1.26ms. See the
Typical Characteristics curve for a graphical guide. The
minimum recommended value for C_SS is 2.2nF.
FB
The feedback (FB) pin is provided for the adjustable
voltage option (no internal connection for fixed options).
This is the control input for programming the output
voltage. A resistor divider network is connected to this pin
from the output and is compared to the internal 0.62V
reference within the regulation loop.
The output voltage can be programmed between 0.65V
and 3.6V using the following equation:
V_OUT
=
V_REF
⋅ 1+

R3 _
R4 _
Where: R3 is the top resistor, R4 is the bottom resistor.
Example feedback resistor values:
VOUT
1.2V
1.5V
1.8V
2.5V
3.3V
R3
274k
316k
560k
324k
464k
R4
294k
221k
294k
107k
107k
September 6, 2013
11
090613-2.0