MIC68401 Datasheet, PDF (10/13 Pages) Micrel Semiconductor – 4A Sequencing LDO with Tracking and Ramp Control™

Micrel, Inc.
Application Information
Enable Input
The MIC68401 features a TTL/CMOS-compatible positive
logic enable input for on/off control of the device. When
the EN input is greater than 1V, it enables the regulator.
When the EN input is less than 0.2V it will disable the
regulator. In shutdown the regulator consumes very little
current (only a few microamperes of leakage).
Input Capacitor
An input capacitor of 10µF or greater is recommended.
The capacitor should be a ceramic X7R type, placed
within 1 inch of the device. Larger values will help to
improve ripple rejection by bypassing the regulator input,
further improving the integrity of the output voltage. If the
output capacitor is > 100µF, then the input capacitor
should be 1/10 the value of the output capacitor in order
to maintain stability during soft-start.
Output Capacitor
The MIC68401 requires an output capacitor for stable
operation. As a µCap LDO, the MIC68401 can operate
with ceramic output capacitors of 10µF or greater with
ESR’s ranging from a 3mΩ to 300mΩ. A general
guideline for calculating the output capacitance is that it
should be greater than 10 µF per amp of output current.
At high frequencies, capacitor values greater than 10µF
improves the transient response while reducing the noise
on the output. X7R dielectric-type ceramic capacitors are
recommended because of their superior temperature
performance. The specific undershoot/overshoot
performance will depend on both the values and
ESR/ESL of the capacitors.
Adjustable Regulator Design
The MIC68401 output voltage can be programmed from
0.5V to 5.5V using a resistor divider from output to the
ADJ pin. Typical sense input currents are less than 30nA
which causes less than 0.3% error with R1 and R2 each
less than or equal to 100kΩ. For large value resistors
(>50KΩ) R1 should be bypassed by a small capacitor
(C_FF = 0.1µF bypass capacitor) to avoid instability due to
phase lag at the ADJ input.
MIC68401
The output resistor divider values are calculated by
Equation 1:
V_OUT
=
0.5V ^R1
 ^R2
+ 1

Eq. 1
Power-on-Reset (POR)
The power-on reset output pin (POR) is an open-drain
N-Channel device that requires a pull-up resistor to a
voltage source. POR is usually connected to the output
voltage (OUT pin). Once the voltage on the internal timer
(DELAY pin) reaches 1.235V, the POR pin is asserted
high. The delay period of the timer begins when the
output voltage is within 10% of its nominal voltage; i.e.,
when the ADJ voltage level exceeds 0.45V. The POR pin
is pulled low when enable (EN) is pulled low or if the
output goes out of regulation by more than 10% due to
loading conditions.
Delay (DELAY)
The MIC68401 is equipped with an internal timer that
delays the assertion of the POR output. The delay is set
by an external capacitor connected from the DELAY pin
to ground. At turn-on, the delay time begins when the EN
pin is high AND the output voltage is within 10% of its
regulation value. Once the DELAY pin reaches 1.235V,
the POR pin asserts high.
The turn on delay (TDLY) is calculated by Equation 2:
T_DELAY
=
(1.235V
)_{}
C_DELAY
1μA

Eq. 2
Scale Factor is:
1.235 seconds/microfarad,
1.235 milliseconds/nanofarad, or
1.235 microseconds/picofarad.
Figure 1. Adjustable Regulator with Resistors
November 7, 2013
10
Revision 1.0