MIC4950 Datasheet, PDF(10/18 Page) Micrel Semiconductor – Hyper Speed Control 5A Buck Regulator

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MIC4950 Datasheet, PDF (10/18 Pages) Micrel Semiconductor – Hyper Speed Control 5A Buck Regulator

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Micrel, Inc.

Functional Description

PVIN

The power input (PVIN) pin provides power to the internal

MOSFETs for the switch mode regulator section of the

MIC4950. The input supply operating range is from 2.7V

to 5.5V. A low-ESR ceramic capacitor of at least 10ÂµF is

required for bypass from PVIN to (Power) GND. See the

âApplications Informationâ section for further details.

AVIN

The analog power input (AVIN) pin provides power to the

internal control and analog supply circuitry. Careful layout

is important to ensure that high-frequency switching noise

caused by PVIN is reduced before reaching AVIN.

Always place a 1ÂµF minimum ceramic capacitor very

close to the IC between AVIN and AGND pins. For

additional high-frequency switching noise attenuation, RC

filtering can be used (R = 10Î©).

A logic high signal on the enable (EN) pin activates the

output of the switch. A logic low on the EN pin

deactivates the output and reduces the supply current to

the nominal 0.01ÂµA. Do not leave this pin floating.

The switch (SW) pin connects directly to one side of the

inductor and provides the current path during switching

cycles. The other end of the inductor is connected to the

load and output capacitor. Due to the high speed

switching on this pin, the switch node should be routed

away from sensitive nodes, whenever possible, to avoid

unwanted injection of noise.

PGND

The power ground (PGND) is the ground return terminal

for the high current in the switching node SW. The

current loop for the PGND should be as short as possible

and kept separate from the AGND net whenever

applicable.

AGND

The analog ground (AGND) is the ground return terminal

for the biasing and control circuitry. The current loop for

the signal ground should be separate from the power

ground (PGND) loop. Refer to the âPCB Layout

Recommendationsâ section for further details.

MIC4950

The power-is-good (PG) pin is an open-drain output that

indicates logic high when the output voltage is typically

above 88% of its steady-state voltage. A pull-up resistor

of 10kÎ© or greater should be connected from PG to

VOUT.

To program the output voltage, an external resistive

divider network is connected to this pin from the output

voltage to AGND, as shown in the Typical Application

circuit on page 1, and is compared to the internal 0.625V

reference within the regulation loop. Equation 1 is used to

program the output voltage:

VOUT

ï½

VREF

ï´ ï§ï¦1ï«

ï¨

R1ï·ï¶

R2ï¸

Eq. 1

Table 1 lists recommended feedback resistor values.

Table 1. Recommended Feedback Resistor Values

VOUT

1.0V

1.2V

1.5V

1.8V

2.5V

3.3V

120kÎ©

274kÎ©

316kÎ©

301kÎ©

316kÎ©

309kÎ©

180kÎ©

294kÎ©

226kÎ©

160kÎ©

105kÎ©

71.5kÎ©

The feedforward capacitor (CF in the Typical Application

schematic) is typically in the range 22pF to 39pF. The

MIC4950 features an internal ripple injection network,

whose current is injected into the FB node and integrated

by CF, thus the waveform at FB is approximately a

triangular ripple. The size of CF dictates the amount of

ripple amplitude at the FB node. Smaller values of CF

yield higher FB ripple amplitude and better stability, but

also somewhat degrade line regulation and transient

response.

Hyper Speed Controlâ¢

MIC4950 uses an ON- and OFF-time proprietary ripple-

based control loop, which features three different timers:

ï· Minimum ON Time

ï· Maximum ON Time

ï· Minimum OFF Time

March 20, 2014

Revision 1.1

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