MIC2184_05 Datasheet, PDF (10/12 Pages) Micrel Semiconductor – Low Voltage Buck PWM Control IC

MIC2184
1.5V
V_IN
Typical
MIC2184
R1
Bias
Circuitry
EN/UVLO
R2
(7)
140mV
Hysteresis
(typical)
Figure 3. UVLO Circuitry
The line voltage turn on trip point is:
V_INPUT
_ ENABLE⁼
V_THRESHOLD
×
R2
R1+ R2
where:
V_THRESHOLD is the voltage level of the internal
comparator reference, typically 1.5V
The input voltage hysteresis is equal to:
V_{INPUT _ HYST}=
V_HYST
×
R1+ R2
R2
where:
V_HYST is the internal comparator hysteresis level,
typically 140mV.
V_{INPUT_HYST} is the hysteresis at the input voltage
The MIC2184 will be disabled when the input voltage drops
back down to:
V_{INPUT_OFF} =
V_{INPUT_ENABLE} – V_{INPUT_HYST} =
(V_THRESHOLD
–
V_HYST)
×
R2
R1+ R2
Either of 2 UVLO conditions will pull the soft start capacitor
low.
• When the V_DD voltage drops below its
undervoltage lockout level.
• When the enable pin drops below the its enable
threshold
The internal bias circuit generates an internal 1.245V band-
gap reference voltage for the voltage error amplifier and a 3V
V_DD voltage for the internal control circuitry. The V_REF pin (pin
13) should be decoupled with a 0.1µf capacitor placed close
to the pin. The V_DD pin must be decoupled with a 1µF ceramic
capacitor. The capacitor must be placed close to the V_DD pin.
The other end of the capacitor must be connected directly to
the ground plane.
MOSFET Gate Drive
The MIC2184 is designed to drive a high side P-channel
MOSFET. The source pin of the P-channel MOSFET is
connected to the input of the power supply. It is turned on
when OUTP pulls the gate of the MOSFET low. The advan-
tage of using a P-channel MOSFET is that it does not require
a bootstrap circuit to boost the gate voltage higher than the
input, as would be required for an N-channel MOSFET.
The V_INP pin (pin 16) supplies the drive voltage to the gate
drive pin, OUTP. V_INP pin is usually connected to the input
Micrel, Inc.
supply. The V_INP pin and CSH pin must be connected to the
same potential.
MOSFET Selection
The P-channel MOSFET must have a V_GS threshold voltage
equal to or lower than the input voltage when used in a buck
converter topology. There is a limit to the maximum gate
charge the MIC2184 will drive. Higher gate charge MOSFET
will slow down the turn-on and turn-off time of the MOSFET.
Slower transition times will cause higher power dissipation in
the MOSFET due to higher switching transition losses.
The MOSFET gate charge is also limited by power dissipation
in the MIC2184. The power dissipated by the gate drive
circuitry is calculated below:
P_{GATE_DRIVE} = Q_GATE × V_INP × f_S
where: Qgate is the total gate charge of both the N and P-
channel MOSFETs.
f_S is the switching frequency
V_INP is the gate drive voltage at the V_INP pin
The graph in Figure 4 shows the total gate charge that can be
driven by the MIC2184 over the input voltage range, for
different values of switching frequency.
200x10^-9
Frequency vs.
Max. Gate Charge
180x10^-9
160x10^-9
140x10^-9
200kHz
120x10^-9
100x10^-9
300kHz
80x10^-9 _500kHz
60x10^-9
400kHz
40x10^-9
600kHz
20x10^-9
0x10⁰_{3 5 7 9 11 13 15 17}
INPUT VOLTAGE (V)
Figure 4. MIC2184 Frequency vs Max. Gate Charge
Oscillator & Sync
The internal oscillator is free running and requires no external
components. The f/2 pin allows the user to select from two
switching frequencies. A low level set the oscillator frequency
to 400kHz and a high level set the oscillator frequency to
200kHz. The maximum duty cycle for both frequencies is
100%. This is another advantage of using a P-channel
MOSFET for the high-side drive; it can continuously turned
on.
A frequency foldback mode is enabled if the voltage on the
feedback pin (pin 6) is less than 0.3V. In frequency foldback,
the oscillator frequency is reduced by approximately a factor
of 4. Frequency foldback is used to limit the energy delivered
to the output during a short circuit fault condition.
The SYNC input (pin 11) lets the MIC2184 synchronize with
an external clock signal. The rising edge of the sync signal
generates a reset signal in the oscillator, which turns off the
low side gate drive output. The high side drive then turns on,
restarting the switching cycle. The sync signal is inhibited
when the controller operates in frequency foldback. The sync
signal frequency must be greater than the maximum speci-
M9999-042205
10
April 2005