MIC2183 Datasheet, PDF (10/12 Pages) Micrel Semiconductor – Low Voltage Synchronous Buck PWM Control IC Final Information

MIC2183
1.5V
V_IN
Typical
MIC2183
R1
Bias
Circuitry
EN/UVLO
R2
(7)
140mV
Hysteresis
(typical)
Figure 3. UVLO Circuitry
The line voltage turn on trip point is:
V_INPUT
_ ENABLE⁼
V_THRESHOLD
×
R2
R1+ R2
where:
V_THRESHOLD is the voltage level of the internal
comparator reference, typically 1.5V
The input voltage hysteresis is equal to:
V_{INPUT _ HYST}=
V_HYST
×
R1+ R2
R2
where:
V_HYST is the internal comparator hysteresis level,
typically 140mV.
V_{INPUT_HYST} is the hysteresis at the input voltage
The MIC2183 will be disabled when the input voltage drops
back down to:
V_{INPUT_OFF} =
V_{INPUT_ENABLE} – V_{INPUT_HYST} =
(V_THRESHOLD
–
V_HYST)
×
R2
R1+ R2
Either of 2 UVLO conditions will pull the soft start capacitor
low.
• When the V_DD voltage drops below its
undervoltage lockout level.
• When the enable pin drops below the its enable
threshold
The internal bias circuit generates an internal 1.245V band-
gap reference voltage for the voltage error amplifier and a 3V
V_DD voltage for the internal control circuitry. The V_DD pin must
be decoupled with a 1µF ceramic capacitor. The capacitor
must be placed close to the V_DD pin. The other end of the
capacitor must be connected directly to the ground plane.
MOSFET Gate Drive
The MIC2183 is designed to drive a high side P-channel
MOSFET and a low side N-channel MOSFET. The source pin
of the P-channel MOSFET is connected to the input of the
power supply. It is turned on when OUTP pulls the gate of the
MOSFET low. The advantage of using a P-channel MOSFET
is that it does not required a bootstrap circuit to boost the gate
voltage higher than the input, as would be required for an N-
channel MOSFET.
The V_INP pin (pin 16) supplies the drive voltage to both gate
drive pins, OUTN and OUTP. V_INP pin is usually connected
Micrel
to the input supply. The V_INP pin and CSH pin must be
connected to the same potential.
A non-overlap time is built into the MOSFET driver circuitry.
This dead-time prevents the high-side and low-side MOSFET
drivers from being on at the same time. Either an external
diode or the low-side MOSFET internal parasitic diode con-
ducts the inductor current during the dead-time.
MOSFET Selection
The P-channel MOSFET must have a V_GS threshold voltage
equal to or lower than the input voltage when used in a buck
converter topology. There is a limit to the maximum gate
charge the MIC2183 will drive. Higher gate charge MOSFETs
will slow down the turn-on and turn-off times of the MOSFETs.
Slower transition times will cause higher power dissipation in
the MOSFETs due to higher switching transition losses. The
MOSFETs must be able to completely turn on and off within
the driver non-overlap time If both MOSFETs are conducting
at the same time, shoot-through will occur, which greatly
increases power dissipation in the MOSFETs and reduces
converter efficiency.
The MOSFET gate charge is also limited by power dissipation
in the MIC2183. The power dissipated by the gate drive
circuitry is calculated below:
P_{GATE_DRIVE} = Q_GATE × V_INP × f_S
where: Qgate is the total gate charge of both the N and P-
channel MOSFETs.
f_S is the switching frequency
V_INP is the gate drive voltage at the V_INP pin
The graph in Figure 4 shows the total gate charge that can be
driven by the MIC2183 over the input voltage range, for
different values of switching frequency.
Frequency vs.
Max. Gate Charge
140
130
200kH
120
110
300kHz
100
90
80 _500kHz
400kHz
70
60
50
600kHz
403 _{5 7 9 11 13 15}
INPUT VOLTAGE (V)
Figure 4. MIC2183 Frequency vs Max. Gate Charge
Oscillator & Sync
The internal oscillator is free running and requires no external
components. The f/2 pin allows the user to select from two
switching frequencies. A low level set the oscillator frequency
to 400kHz and a high level set the oscillator frequency to
200kHz. The maximum duty cycle for both frequencies is
100%. This is another advantage of using a P-channel
MOSFET for the high-side drive; it can continuously turned
on.
A frequency foldback mode is enabled if the voltage on the
feedback pin (pin 6) is less than 0.3V. In frequency foldback,
MIC2183
10
December 10, 2001