SY89876L_0708 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS

Micrel, Inc.
3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS
PROGRAMMABLE CLOCK DIVIDER AND
Precision Edge^®
Precision E^SYd⁸g⁹e^87®6L
1:2 FANOUT BUFFER W/ INTERNAL TERMINATION ^SY89876L
FEATURES
DESCRIPTION
„ Integrated programmable clock divider and 1:2
fanout buffer
„ Guaranteed AC performance over temperature and
voltage:
• >2.0GHz f_MAX
• <190ps t_r / t_f
• <15ps within device skew
„ Low jitter design:
• <10ps_PP total jitter
• <1ps_RMS cycle-to-cycle jitter
„ Unique input termination and VT Pin for DC- and AC-
coupled inputs; CML, PECL, LVDS and HSTL
„ LVDS-compatible outputs
„ TTL/CMOS inputs for select and reset
„ Parallel programming capability
„ Programmable divider ratios of 1, 2, 4, 8 and 16
„ Low voltage operation 3.3V
„ Output disable function
„ –40°C to 85°C industrial temperature range
„ Available in 16-pin (3mm x 3mm) MLF^® package
APPLICATIONS
„ SONET/SDH line cards
„ Transponders
„ High-end, multiprocessor servers
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V_REF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
FUNCTIONAL BLOCK DIAGRAM
CML/LVPECL/LVDS
622MHz
Clock In
Divide-by-4
LVDS
155.5MHz
Clock Out
S2
(TTL/CMOS)
/RESET
(TTL/CMOS)
Enable
FF
Enable
Q0
MUX
/Q0
MUX
IN
50Ω
V_T
50Ω
/IN
Q1
Divided
by
/Q1
2, 4, 8
or 16
S1
(TTL/CMOS)
S0
(TTL/CMOS)
V_{REF_AC}
Decoder
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
[e-mail] or [phone]
1
IN
/IN
Q0
/Q0
622MHz In
155.5MHz Out
Rev.: E Amendment: /0
Issue Date: August 2007