SY89875U_07 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS PROGRAMMABLE CLOCK DIVIDER AND 1:2 FANOUT BUFFER W/ INTERNAL TERMINATION

Micrel, Inc.
2.5V, 2.0GHz ANY DIFF. IN-TO-LVDS
Precision Edge^®
Precision E^Sd^Y8g⁹e^8®75U
PROGRAMMABLE CLOCK DIVIDER AND 1:2
SY89875U
FANOUT BUFFER W/ INTERNAL TERMINATION
FEATURES
DESCRIPTION
■ Integrated programmable clock divider and 1:2
fanout buffer
■ Guaranteed AC performance over temperature and
voltage:
• > 2.0GHz f_MAX
• < 200ps t_r/t_f
• < 15ps within device skew
■ Low jitter design:
• < 10ps_PP total jitter
• < 1ps_RMS cycle-to-cycle jitter
■ Unique input termination and V_T Pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
■ LVDS compatible outputs
■ TTL/CMOS inputs for select and reset
■ Parallel programming capability
■ Programmable divider ratios of 1, 2, 4, 8 and 16
■ Low voltage operation 2.5V
■ Output disable function
■ –40°C to 85°C temperature range
■ Available in 16-pin (3mm × 3mm) MLF^® package
APPLICATIONS
■ SONET/SDH line cards
■ Transponders
■ High-end, multiprocessor servers
FUNCTIONAL BLOCK DIAGRAM
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS
or HSTL clock input signal and dividing down the frequency
using a programmable divider to create a lower speed
version of the input clock. Available divider ratios are 2, 4, 8
and 16, or straight pass-through.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a V_T pin. This feature allows the device to
easily interface to different logic standards. A V_REF-AC
reference is included for AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /IN).
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
CML/LVPECL/LVDS
622MHz
Clock In
Divide-by-4
LVDS
155.5MHz
Clock Out
S2
/RESET
Enable
FF
Enable
MUX
IN
9 50
V_T
9 50
/IN
S1
S0
Decoder
Divided
by
2, 4, 8
or 16
MUX
Q0
/Q0
Q1
/Q1
V_{REF_AC}
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-020707
[e-mail] or [phone]
1
IN
/IN
Q0
/Q0
622MHz In
155.5MHz Out
Rev.: C Amendment: /0
Issue Date: February 2007