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SY89874U_07 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION | |||
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Micrel, Inc.
2.5GHz ANY DIFF. IN-TO-LVPECL
Precision Edge®
Precision ESdY8g9e8®74U
PROGRAMMABLE CLOCK DIVIDER/
SY89874U
FANOUT BUFFER WITH INTERNAL TERMINATION
FEATURES
â Integrated programmable clock divider and 1:2
fanout buffer
â Guaranteed AC performance over temperature and
voltage:
⢠> 2.5GHz fMAX
⢠< 250ps tr/tf
⢠< 15ps within device skew
â Low jitter design:
⢠< 10psPP total jitter
⢠< 1psRMS cycle-to-cycle jitter
â Unique input termination and VT pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
â TTL/CMOS inputs for select and reset
â 100k EP compatible LVPECL outputs
â Parallel programming capability
â Programmable divider ratios of 1, 2, 4, 8 and 16
â Low voltage operation 2.5V or 3.3V
â Output disable function
â â40°C to 85°C temperature range
â Available in 16-pin (3mm à 3mm) MLF® package
Precision Edge®
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or
HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked, lower speed version of the input clock. Available divider
ratios are 2, 4, 8 and 16, or straight pass-through. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
different logic standards. A VREF-AC reference is included for
AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N).
APPLICATIONS
â SONET/SDH line cards
â Transponders
â High-end, multiprocessor sensors
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
FUNCTIONAL BLOCK DIAGRAM
S2
LVDS
622MHz
Clock In
Divide-by-4
LVPECL
155.5MHz
Clock Out
/RESET
Enable
FF
Enable
Q0
MUX
/Q0
IN
MUX
IN
R0
VT
R1
/IN
S0
S1
Decoder
Divided
by
2, 4, 8
or 16
Q1
/Q1
/IN
Q0
VREF-AC
/Q0
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-020707
hbwhelp@micrel.com or (408) 955-1690
1
622MHz In
155.5MHz Out
Rev.: D Amendment: /0
Issue Date: February 2007
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