SY89874U Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/FANOUT BUFFER WITH INTERNAL TERMINATION

2.5GHz ANY DIFF. IN-TO-LVPECL
Precision Edge™
PROGRAMMABLE CLOCK DIVIDER/FANOUT ^SY89874U
BUFFER WITH INTERNAL TERMINATION
FINAL
FEATURES
I Integrated programmable clock divider and 1:2
fanout buffer
I Guaranteed AC performance over temperature and
voltage:
• > 2.5GHz f_MAX
• < 250ps t_r/t_f
• < 15ps within device skew
I Low jitter design:
• < 10ps (pk-pk) total jitter
• < 1ps (rms) cycle-to-cycle jitter
I Unique input termination and V_T pin for DC-coupled
and AC-coupled Inputs; CML, PECL, LVDS and
HSTL
I TTL/CMOS inputs for select and reset
I 100k EP compatible LVPECL outputs
I Parallel programming capability
I Programmable divider ratios of 1, 2, 4, 8 and 16
I Low voltage operation 2.5V or 3.3V
I Output disable function
I –40°C to 85°C temperature range
I Available in 16-pin (3mm × 3mm) MLF™ package
Precision Edge™
DESCRIPTION
This low-skew, low-jitter device is capable of accepting a
high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or
HSTL clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked, lower speed version of the input clock. Available divider
ratios are 2, 4, 8 and 16, or straight pass-through. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a V_T pin. This feature allows the device to easily interface to
different logic standards. A V_REF-AC reference is included for
AC-coupled applications.
The /RESET input asynchronously resets the divider. In
the pass-through function (divide by 1) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N).
APPLICATIONS
I SONET/SDH line cards
I Transponders
I High-end, multiprocessor sensors
TYPICAL PERFORMANCE
OC-12 to OC-3
Translator/Divider
FUNCTIONAL BLOCK DIAGRAM
S2
LVDS
622MHz
Clock In
Divide-by-4
LVPECL
155.5MHz
Clock Out
/RESET
Enable
FF
Enable
Q0
MUX
/Q0
IN
MUX
IN
R0
V_T
R1
/IN
S0
S1
Decoder
Divided
by
2, 4, 8
or 16
Q1
/Q1
/IN
Q0
V_REF-AC
/Q0
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
1
622MHz In
155.5MHz Out
Rev.: B Amendment: /1
Issue Date: February 2003