SY89873L_0708 Datasheet, PDF (1/11 Pages) Micrel Semiconductor – 3.3V, 2.0GHz ANY DIFF. IN-TO-LVDS

Micrel, Inc.
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FEATURES
■ Guaranteed AC performance
• > 2.0GHz f_MAX output toggle
• > 3.0GHz f_MAX input
• < 800ps t_PD (matched-delay between banks)
• < 15ps within-device skew
• < 190ps rise/fall time
■ Low jitter design
• < 1ps_RMS cycle-to-cycle jitter
• < 10ps_PP total jitter
■ Unique input termination and V_T pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
■ Precision differential LVDS outputs
■ Matched delay: all outputs have matched delay,
independent of divider setting
■ TTL/CMOS inputs for select and reset/disable
■ Two LVDS output banks (matched delay)
• Bank A: Buffered copy of input clock (undivided)
• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
two copies
■ 3.3V power supply
■ Wide operating temperature range: –40°C to +85°C
■ Available in 16-pin (3mm × 3mm) MLF^® package
APPLICATIONS
■ SONET/SDH line cards
■ Transponders
■ High-end, multiprocessor servers
Precision Edge^®
DESCRIPTION
This 3.3V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC- or
DC-coupled) CML, LVPECL, HSTL or LVDS and divides down
the frequency using a programmable divider ratio to create a
frequency-locked, lower speed version of the input clock. The
SY89873L includes two output banks. Bank A is an exact
copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank. Available
divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz,
77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination
design that allows access to the termination network through
a VT pin. This feature allows the device to easily interface to
all AC- or DC-coupled differential logic standards. A V_REF-AC
reference is included for AC-coupled applications.
The SY89873L is part of Micrel’s high-speed Precision
Edge^® timing and distribution family. For 2.5V applications,
consider the SY89872U. For applications that require an
LVPECL output, consider the SY89871U.
The /RESET input asynchronously resets the divider outputs
(Bank B). In the pass-through function (Bank A) the /RESET
synchronously enables or disables the outputs on the next
falling edge of IN (rising edge of /N). Refer to the Timing
Diagram.
All support documentation can be found on Micrel’s web
site at: www.micrel.com.
FUNCTIONAL BLOCK DIAGRAM
TYPICAL APPLICATION
/RESET
V_REF-AC
IN
50Ω
V_T
50Ω
/IN
Enable
FF
Enable
MUX
Divided
by
2, 4, 8
or 16
622MHz/155.5MHz
SONET Clock Generator
QA
QA 622MHz LVDS
/QA
OC-12 or
/QA Clock Out
622MHz LVPECL IN
OC-3
QB0
Clock In /IN
Clock Gen
QB 155.5MHz LVDS
/QB0
/QB Clock Out
QB1
Bank B: 155.5MHz: For OC-3 line card
/QB1
Set to divide-by-4
S0
Decoder
S1
Bank A: 622MHz: For OC-12 line card
Set to pass-through
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
[e-mail] or [phone]
1
Rev.: F Amendment: /0
Issue Date: February 2007