SY89872U_0708 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 2.5V, 2GHz ANY DIFF. IN-TO-LVDS

Micrel, Inc.
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FEATURES
„ Guaranteed AC performance over temperature and
voltage:
• >2GHz f_MAX
• < 750ps t_PD (matched delay between banks)
• < 15ps within-device skew
• < 200ps rise/fall time
„ Low jitter design
• < 1ps_RMS cycle-to-cycle jitter
• < 10ps_PP total jitter
„ Unique input termination and VT pin for DC-coupled
and AC-coupled inputs: any differential inputs
(LVPECL, LVDS, CML, HSTL)
„ Precision differential LVDS outputs
„ Matched delay: all outputs have matched delay,
independent of divider setting
„ TTL/CMOS inputs for select and reset/disable
„ Two output banks (matched delay)
• Bank A: Buffered copy of input clock (undivided)
• Bank B: Divided output (÷2, ÷4, ÷8, ÷16),
two copies
„ 2.5V power supply
„ Wide operating temperature range: –40°C to +85°C
„ Available in 16-pin (3mm x 3mm) MLF^® package
APPLICATIONS
„ OC-3 to OC-192 SONET/SDH applications
„ Transponders
„ Oscillators
„ SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
Precision Edge^®
DESCRIPTION
This 2.5V low-skew, low-jitter, precision LVDS output clock
divider accepts any high-speed differential clock input (AC
or DC-coupled) CML, LVPECL, HSTL or LVDS and divides
down the frequency using a programmable divider ratio to
create a frequency-locked, lower speed version of the input
clock. The SY89872U includes two output banks. Bank A is
an exact copy of the input clock (pass through) with matched
propagation delay to Bank B, the divided output bank.
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a V_T pin. This feature allows the device to
easily interface to different logic standards. A V_REF-AC
reference is included for AC-coupled applications.
The SY89872U is part of Micrel’s high-speed Precision
Edge^® timing and distribution family. For 3.3V applications,
consider the SY89873L. For applications that require an
LVPECL output, consider the SY89872U.
The /RESET input asynchronously resets the divider
outputs (Bank B). In the pass-through function (Bank A) the
/RESET synchronously enables or disables the outputs on
the next falling edge of IN (rising edge of /IN). Refer to the
“Timing Diagram.”
TYPICAL APPLICATION
/RESET,
/DISABLE
Enable
FF
IN
50Ω
V_T
50Ω
/IN
V_REF-AC
S1
S0
Decoder
Enable
MUX
Divided
by
2, 4, 8
or 16
622MHz/155.5MHz
SONET Clock Generator
QA
622MHz LVPECL
QA _{622MHz LVDS}
/QA
Clock In
/QA Clock Out
IN
OC-12 or OC-3
QB0
/IN
Clock Generator
QB 155.5MHz LVDS
/QB0
/QB ^{Clock Out}
QB1
/QB1
Bank A: 622MHz for OC-12 line card
Bank B: 155.5MHz for OC-3 line card (set to divide-by-4)
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082407
[e-mail] or [phone]
1
Rev.: F Amendment: /0
Issue Date: August 2007