SY89871U Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 2.5GHz ANY DIFF. IN-TO-LVPECL PROGRAMMABLE CLOCK DIVIDER/ FANOUT BUFFER WI/INTERNAL TERMINATION

Micrel
2.5GHz ANY DIFF. IN-TO-LVPECL
PROGRAMMABLE CLOCK DIVIDER/
Precision Edge™
Precision E^Sd^Yg⁸e⁹™^871U
FANOUT BUFFER W/INTERNAL TERMINATION
SY89871U
FEATURES
s Two matched-delay outputs:
• Bank A: undivided pass-through (QA)
• Bank B: programmable divide by
2, 4, 8, 16 (QB0, QB1)
s Matched delay: all outputs have matched delay,
independent of divider setting
s Guaranteed AC performance:
• >2.5GHz f_MAX
• <250ps t_r/t_f
• <670ps t_pd (matched delay)
• <15ps within-device skew
s Low jitter design
• <1ps_rms cycle-to-cycle jitter
• <10ps_pp total jitter
s Power supply 3.3V or 2.5V
s Unique patent-pending input termination and VT pin
for DC-coupled and AC-coupled inputs: any
differential inputs (LVPECL, LVDS, CML, HSTL)
s TTL/CMOS inputs for select and reset
s 100K EP compatible LVPECL outputs
s Parallel programming capability
s Wide operating temperature range: –40°C to +85°C
s Available in 16-pin (3mm × 3mm) MLF™ package
APPLICATIONS
s OC-3 to OC-192 SONET/SDH applications
s Transponders
s Oscillators
s SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
V_REF-AC
IN
50Ω
V_T
50Ω
/IN
S0
Decoder
S1
Divided
by
2, 4, 8
or 16
QA
/QA
QB0
/QB0
QB1
/QB1
Precision Edge™
DESCRIPTION
The SY89871U is a 2.5V/3.3V LVPECL output precision
clock divider capable of accepting a high-speed differential
clock input (AC or DC-coupled) CML, LVPECL, HSTL or
LVDS clock input signal and dividing down the frequency
using a programmable divider ratio to create a frequency-
locked lower speed version of the input clock (Bank B).
Available divider ratios are 2, 4, 8 and 16. In a typical
622MHz clock system this would provide availability of
311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock
components.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards. A V_REF-AC
reference is included for AC-coupled applications.
The SY89871U includes two phase-matched output
banks. Bank A (QA) is a frequency-matched copy of the
input. Bank B (QB0, QB1) is a divided down output of the
input frequency. Bank A and Bank B maintain a matched
delay independent of the divider setting.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
TYPICAL PERFORMANCE
QA
622MHz
Output
/QA
QB0
155.5MHz
Output
QA@622MHz and QB@155.5MHz
Ö4
/RESET
/QB0
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-062904
[e-mail] or [phone]
1
Rev.: C Amendment: /0
Issue Date: June 2004