SY89827L_10 Datasheet, PDF (1/11 Pages) Micrel Semiconductor – 3.3V 500MHz DUAL 1:10 HSTL FANOUT BUFFER/TRANSLATOR WITH 2:1 MUX INPUT

Micrel, Inc.
3.3V 500MHz DUAL 1:10 HSTL FANOUT
Precision Edge^®
Precision E^Sd^Yg⁸⁹e^8®27L
BUFFER/TRANSLATOR WITH 2:1 MUX INPUT ^SY89827L
FEATURES
■ Dual LVPECL or HSTL input, 10 differential 1.5V
HSTL compatible outputs
■ Configurable as dual-channel 10 output or a single-
channel 20 output clock driver
■ Guaranteed AC parameters over temperature and
voltage:
• > 500MHz f_MAX
• < 50ps within device skew
• < 1.5ns propagation delay
• < 700ps t_r / t_f time
■ Low jitter design
• 186fs_RMS phase jitter
■ 3.3V core supply, 1.8V output supply
■ Output enable function
■ Available in a 64-Pin EPAD-TQFP
APPLICATIONS
■ High-performance PCs
■ Workstations
■ Parallel processor-based systems
■ Other high-performance computing
■ Communications
DESCRIPTION
Precision Edge^®
The SY89827L is a High Performance Bus Clock
Driver with dual 1:10 or single 1:20 HSTL (High Speed
Transceiver Logic) output pairs. The part is designed for
use in low voltage (3.3V/1.8V) applications which require a
large number of outputs to drive precisely aligned, ultra low
skew signals to their destination. The input is multiplexed
from either HSTL or LVPECL (Low Voltage Positive Emitter
Coupled Logic) by the CLK_SEL pin. The Output Enables
(OE1 & OE2) are synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse
when the device is enabled/disabled as can happen with an
asynchronous control.
The SY89827L features extremely low skew performance
of <50ps over temperature and voltage –performance
previously unachievable in a standard product having such
a high number of outputs. The SY89827L is available in a
single space saving package, enabling a lower overall cost
solution. For applications that require greater HSTL fanout
capability, consider the SY89824L.
TYPICAL APPLICATION CIRCUIT
Primary Clock Source
LVPECL_CLKA
/LVPECL_CLKA
Redundant Backup
Clock Source
LVPECL_CLKB
/LVPECL_CLKB
10
Primary
10
Card
10
Redundant
10
Card
SEL1
Primary/Backup Clock Select
(Switchover within 2.0ns)
System using SY89827L as a switchover circuit from a Primary Clock to a Redundant Backup Clock in a failsafe application.
LVPECL inputs only, shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-073010
[e-mail] or [phone]
1
Rev.: F
Amendment: /0
Issue Date: July 2010