SY89826L Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 3.3V 1GHz PRECISION 1:22 LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX

Micrel, Inc.
3.3V 1GHz PRECISION 1:22 LVDS
FANOUT BUFFER/TRANSLATOR
WITH 2:1 INPUT MUX
Precision Edge^®
Precision E^Sd^Yg⁸⁹e^8®26L
SY89826L
FEATURES
s High-performance, 1GHz LVDS fanout buffer/
translator
s 22 differential LVDS output pairs
s Guaranteed AC parameters over temperature and
voltage:
• > 1GHz f_MAX
• < 50ps within device skew
• < 400ps t_r / t_f time
s Low jitter performance
• < 1ps (rms) cycle-to-cycle jitter
• < 1ps (pk-pk) total jitter
s 2:1 mux input accepts LVDS and LVPECL
3.3V supply voltage
s LVDS input includes internal 100Ω termination
s Output enable function
s Available in a 64-Pin EPAD-TQFP
APPLICATIONS
s Enterprise networking
s High-end servers
s Communications
Precision Edge^®
DESCRIPTION
The SY89826L is a precision fanout buffer with 22
differential LVDS (Low Voltage Differential Swing) output
pairs. The part is designed for use in low voltage 3.3V
applications that require a large number of outputs to drive
precisely aligned, ultra low-skew signals to their destination.
The input is multiplexed from either LVDS or LVPECL (Low
Voltage Positive Emitter Coupled Logic) by the CLK_SEL
pin. The OE (Output Enable) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control.
The SY89826L features a low pin-to-pin skew of less
than 50ps—performance previously unachievable in a
standard product having such a high number of outputs.
The SY89826L is available in a single space saving package,
enabling a lower overall cost solution.
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
100Ω internal input
termination
LVDS_CLK
/LVDS_CLK
CLK_SEL
0
LVPECL_CLK
/LVPECL_CLK
1
LEN Q
22 LVDS compatible
outputs
22
Q0 - Q21
22
/Q0 - /Q21
OE⁽¹⁾
0
0
1
1
CLK_SEL
0
1
0
1
Q0 – Q21
LOW
LOW
LVDS_CLK
LVPECL_CLK
/Q0 – /Q21
HIGH
HIGH
/LVDS_CLK
/LVPECL_CLK
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
LVDS_CLK and LVPECL_CLK signal.
OE D
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011907
[e-mail] or [phone]
1
Rev.: D Amendment: /0
Issue Date: January 2007