SY89823L Datasheet, PDF (1/8 Pages) Micrel Semiconductor – 3.3V, 500MHz 1:22 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR

Micrel, Inc.
3.3V, 500MHz 1:22
DIFFERENTIAL HSTL (1.5V)
FANOUT BUFFER/TRANSLATOR
Precision Edge^®
Precision E^Sd^Y8g⁹e^82®3L
SY89823L
FEATURES
s 22 differential HSTL (low-voltage swing) output pairs
s HSTL outputs drive 50Ω to ground with no offset
voltage
s 3.3V core supply, 1.8V output supply for reduced
power
s LVPECL and HSTL inputs
s Low part-to-part skew (200ps max.)
s Low pin-to-pin skew (50ps max.)
s Triple-buffered output enable (OE)
s –40°C to +85°C temperature range
s Available in a 64-pin EPAD-TQFP
APPLICATIONS
s High-performance PCs
s Workstations
s Parallel processor-based systems
s Other high-performance computing
s Communications
Precision Edge^®
DESCRIPTION
The SY89823L is a high-performance bus clock driver with 22
differential High-Speed Transceiver Logic (HSTL), 1.5V compatible
output pairs. The device is designed for use in low-voltage (3.3V/
1.8V) applications that require a large number of outputs to drive
precisely aligned, ultra-low skew signals to their destination. The
input is multiplexed from either HSTL or Low-Voltage Positive-
Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin.
The Output Enable (OE) is synchronous and triple-buffered so
that the outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any potential of generating a runt clock
pulse when the device is enabled/disabled, as can occur with an
asynchronous control. The triple-buffering feature provides a three-
clock delay from the time the OE input is asserted/de-asserted to
when the clock appears at the outputs.
The SY89823L features low pin-to-pin skew (50ps max.) and low
part-to-part skew (200ps max.), performance previously unachievable
in a standard product having such a high number of outputs. The
SY89823L is available in a single, space-saving package, enabling
a lower overall cost solution.
All support documentation can be found on Micrel’s web site at:
www.micrel.com.
LOGIC SYMBOL
TRUTH TABLE
CLK_SEL
HSTL_CLK
/HSTL_CLK
LVPECL_CLK
/LVPECL_CLK
OE
0
22
Q0 - Q21
22
/Q0 - /Q21
1
EN
ENABLE
LOGIC
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011907
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OE⁽¹⁾
0
0
1
1
CLK_SEL
0
1
0
1
Q₀-Q₂₁
LOW
LOW
HSTL_CLK
LVPECL_CLK
/Q₀-/Q₂₁
HIGH
HIGH
/HSTL_CLK
/LVPECL_CLK
Note:
1. The output enable (OE) signal is synchronized with the low level of the
HSTL_CLK and LVPECL_CLK signal.
TYPICAL PERFORMANCE
Output Amplitude
900
vs. Frequency
800
700
600
500
400
300
200
100
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
OUTPUT FREQUENCY (GHz)
Rev.: C Amendment: /0
1
Issue Date: January 2007