SY89809L_05 Datasheet, PDF (1/7 Pages) Micrel Semiconductor – 3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

Micrel, Inc.
3.3V 1:9 HIGH-PERFORMANCE,
LOW-VOLTAGE BUS CLOCK DRIVER
Precision Edge^®
Precision E^Sd^Yg⁸⁹e^8®09L
SY89809L
FEATURES
s 3.3V core supply, 1.8V output supply for reduced
power
s LVPECL and HSTL inputs
s 9 differential HSTL (low-voltage swing) output pairs
s HSTL outputs drive 50Ω to ground with no
offset voltage
s 500MHz maximum clock frequency
s Low part-to-part skew (200ps max.)
s Low pin-to-pin skew (50ps max.)
s Available in 32-pin TQFP package
LOGIC SYMBOL
CLK_SEL
HSTL_CLK
/HSTL_CLK
0
LVPECL_CLK
1
/LVPECL_CLK
OE
LEN
Q
D
9
Q0 – Q8
9
/Q0 – /Q8
Precision Edge^®
DESCRIPTION
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultralow skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
APPLICATIONS
s High-performance PCs
s Workstations
s Parallel processor-based systems
s Other high-performance computing
s Communications
TRUTH TABLE
OE⁽¹⁾
0
CLK_SEL
0
Q₀ – Q₈
LOW
/Q₀ – /Q₈
HIGH
0
1
LOW
HIGH
1
0
HSTL_CLK
/HSTL_CLK
1
1
LVPECL_CLK /LVPECL_CLK
Note:
1. The OE (output enable) signal is synchronized with the low level of the
HSTL_CLK and LVPECL_CLK signal.
SIGNAL GROUPS
Level
HSTL
HSTL
LVPECL
LVCMOS/LVTTL
Direction
Input
Output
Input
Input
Signal
HSTL_CLK, /HSTL_CLK
Q₀ – Q₈, /Q₀ – /Q₈
LVPECL_CLK, /LVPECL_CLK
CLK_SEL, OE
Precision Edge is a registered trademark of Micrel, Inc.
M9999-092005
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1
Rev.: E Amendment: /0
Issue Date: September 2005