SY89809L Datasheet, PDF (1/4 Pages) Micrel Semiconductor – 3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER

3.3V 1:9 HIGH-PERFORMANCE,
LOW-VOLTAGE
BUS CLOCK DRIVER
ClockWorks™
SY89809L
FEATURES
s 3.3V core supply, 1.8V output supply for reduced
power
s LVPECL and HSTL inputs
s 9 differential HSTL (low-voltage swing) output pairs
s HSTL outputs drive 50Ω to ground with no
offset voltage
s 500MHz maximum clock frequency
s Low part-to-part skew (200ps max.)
s Low pin-to-pin skew (50ps max.)
s Available in 32-pin TQFP package
PIN CONFIGURATION
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
Top View
21
5
TQFP
T32-1
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
VCCO
Q3
Q3
Q4
Q4
Q5
Q5
VCCO
DESCRIPTION
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultralow skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
APPLICATIONS
s High-performance PCs
s Workstations
s Parallel processor-based systems
s Other high-performance computing
s Communications
PIN NAMES
Pin
HSTL_CLK, /HSTL_CLK
LVPECL_CLK, /LVPECL_CLK
CLK_SEL
OE
Q₀-Q₈, /Q₀-/Q₈
GND
V_CCI
V_CCO
Function
Differential HSTL Inputs
Differential LVPECL Inputs
Input CLK Select (LVTTL)
Output Enable (LVTTL)
Differential HSTL Outputs
Ground
V_CC Core
V_CC Output
LOGIC SYMBOL
CLK_SEL
HSTL_CLK
HSTL_CLK
0
LVPECL_CLK
1
LVPECL_CLK
OE
LEN
Q
D
9
Q0 – Q8
9
Q0 – Q8
Rev.: A Amendment: /0
1
Issue Date: March 2000