SY89426 Datasheet, PDF (1/6 Pages) Micrel Semiconductor – SONET OC-12/OC-3 CLOCK SYNTHESIZER

SONET OC-12/OC-3
CLOCK SYNTHESIZER
ClockWorks™
SY89426
FEATURES
s Single chip source for 622.08MHz and 155.52MHz
clocks
s 622.08MHz output is differential PECL, 155.52MHz
output is single-ended PECL
s TTL/CMOS compatible inputs and reference output
s SONET compliant jitter performance (≤0.01UI)
s Choice of three reference frequencies
s Only 395mW (typ)
s Complies with Bellcore, CCITT and ANSI standards
s Single +5 volt power supply
s Fully compatible with industry standard 10KH I/O
levels
s Available in 28-pin PLCC package
DESCRIPTION
Micrel-Synergy's SY89426 Multi-Output Phase Locked
Loop (PLL) is a SONET compliant clock generator providing
622.08MHz, 155.52MHz and retimed reference clock
outputs. The PLL produces low jitter OC-12/STS-12 and
OC-3/STS-3 rate clocks from an input reference clock of
38.88, 51.84, or 77.76MHz. Additionally, the input reference
clock is retimed and provided as a TTL/CMOS compatible
output, which may be disabled to minimize switching noise.
The SY89426 operates from a single +5 volt supply, and
requires only a simple series RC loop filter.
Coupling Micrel-Synergy's advanced PLL technology
with our proprietary ASSET™ bipolar process has produced
a clock generator IC which exceeds applicable Bellcore
and ANSI specifications, while setting a new standard for
performance and flexibility.
TYPICAL APPLICATION
PIN CONFIGURATION
+5V +5V
+3V
VCC VCCO
CLOCK
IN
RFCK
(TTL)
CK622P
(PECL)
CK622N
0.1uF
FLTRN
1000Ω
FLTRP ^SY89426
SEL39
(TTL)
SEL78
(TTL)
GND
CK155
(PECL)
RETRFCK
(TTL)
RST DISC
(TTL) (TTL)
2X 50Ω
622.08MHz
CLOCK OUT
+3V
50Ω
155.52MHz
CLOCK OUT
RETIMED
REFOUT
GND
GND
SEL39
SEL78
RFCK
VCC
NC
25 24 23 22 21 20 19
26
18
27
17
28
PLCC
16
1
TOP VIEW
15
J28-1
2
14
3
13
4
12
5 6 7 8 9 10 11
VCC
VCC
CK622P
CK622N
VCCO
CK155
GND
Rev.: F Amendment: /0
1
Issue Date: July, 1999