SY89113U_07 Datasheet, PDF (1/14 Pages) Micrel Semiconductor – 2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination

SY89113U
2.5V Low Jitter, Low Skew 1:12 LVDS
Fanout Buffer with 2:1 Input MUX and
Internal Termination
General Description
The SY89113U is a 2.5V low jitter, low skew, 1:12
LVDS fanout buffer optimized for precision telecom
and enterprise server distribution applications. The
input includes a 2:1 MUX for clock switchover
applications. Unlike other multiplexers, this input
includes a unique isolation design that minimizes
channel-to-channel crosstalk. The SY89113U
distributes clock frequencies from DC to >1GHz
guaranteed over temperature and voltage. The
SY89113U incorporates a synchronous output enable
(EN) so that the outputs will only be enabled/disabled
when they are already in the LOW state.
CLK0 differential input includes Micrel's unique, 3-pin
input termination architecture that directly interfaces to
any differential signal (AC- or DC-coupled) as small as
100mV (200mV_PP) without any level shifting or
termination resistor networks in the signal path.
CLK1 differential input includes a new version of
Micrel's unique, Any-Input architecture that directly
interfaces with single-ended TTL/CMOS logic
(including 3.3V logic), single-ended LVPECL,
differential (AC- or DC-coupled) LVDS, HSTL, CML,
and LVPECL logic levels as small as 200mV
(400mV_PP). CLK1 input requires external termination.
LVDS output swing 325mV into 10Ω0 with extremely
fast rise/fall time guaranteed to be less than 250ps.
The SY89113U operates from a 2.5V±5% supply and
is guaranteed over the full industrial temperature
range of -40°C to +85°C. The SY89113U is part of
Micrel's high-speed, Precision Edge^® product line.
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
Features
Precision Edge^®
• Selects between 1 of 2 inputs, and provides 12
precision, low skew LVDS output copies
• Guaranteed AC performance over temperature and
voltage:
– DC to >1GHz throughput
– <975ps propagation delay CLK0-to-Q
– <250ps rise/fall time
– <25ps output-to-output skew
• Ultra-low jitter design:
– <1ps_RMS random jitter
– <10ps_PP total jitter (clock)
– <1ps_RMS cycle-to-cycle jitter
– <0.7ps_RMS crosstalk induced jitter
• Unique, patent-pending 2:1 input MUX provides
superior isolation to minimize channel-to-channel
crosstalk
• CLK0 input features a unique, patent-pending input
termination and VT pin that accepts AC- and DC-
coupled inputs (CML, LVPECL, LVDS)
• CLK1 accepts virtually any logic standard:
– Single-ended: TTL/CMOS (including 3.3V logic),
LVPECL
– Differential: LVPECL, LVDS, CML, HSTL
• 325mV LVDS-compatible output swing
• Power supply: 2.5V +5%
• Industrial temperature range –40°C to +85°C
• Available in 44-pin (7mm x 7mm) QFN package
Applications
• Multi-processor server
• SONET/SDH clock/data distribution
• Fibre Channel distribution
• Gigabit Ethernet clock distribution
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax + 1 [phone] • http://www.micrel.com
December 2007
M9999-120607
[e-mail] or [phone]